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200-mbaud hotlink? transceiver cy7c924dx cypress semiconductor corporation 3901 north first street san jose ca 95134 408-943-2600 june 14, 2000 features ? second-generation hotlink? technology fibre channel and escon? compliant 8b/10b encoder/decoder 10- or 12-bit pre-encoded data path (raw mode) 8- or 10-bit encoded data transport (using 8b/10b coding) parity check/generate synchronous or asynchronous ttl parallel interface utopia compatible host bus interface embedded/bypassable 256-character synchronous fifos integrated support for daisy-chain and ring topologies domain or individual destination device addressing 50- to 200-mbaud serial signaling rate internal plls with no external pll components dual differential pecl serial inputs dual differential pecl serial outputs compatible with fiber-optic modules and copper cables built-in self-test (bist) for link testing link quality indicator single +5.0v 10% supply 100-pin tqfp 0.35 cmos technology functional description the 200-mbaud cy7c924dx hotlink transceiver is a point- to-point communications building block allowing the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper transmission lines) at speeds ranging be- tween 50 and 200 mbaud. the transmit section accepts par- allel data of selectable width and converts it to serial data, while the receiver section accepts serial data and converts it to parallel data of selectable width. figure 1 illustrates typical connections between two independent host systems and cor- responding cy7c924dx parts. as a second generation hotlink device, the cy7c924dx provides enhanced levels of technology, functionality, and integration over the field-proven cy7b923/933 hotlink. the transmit section of the cy7c924dx hotlink can be con- figured to accept either 8- or 10-bit data characters on each clock cycle, and stores the parallel data into an internal trans- mit fifo. data is read from the transmit fifo and is encoded using an embedded 8b/10b encoder to improve its serial transmission characteristics. these encoded characters are then serialized and output from two positive ecl (pecl) com- patible differential transmission line drivers at a bit-rate of 10 times the input reference clock. the receive section of the cy7c924dx hotlink accepts a serial bit-stream from one of two pecl-compatible differential line receivers and, using a completely integrated pll clock synchronizer, recovers the timing information necessary for data reconstruction. the recovered bit stream is deserialized and framed into characters, 8b/10b decoded, and checked for transmission errors. recovered decoded characters are re- constructed into either 8- or 10-bit data characters, written to an internal receive fifo, and presented to the destination host system. the integrated 8b/10b encoder/decoder may be bypassed for systems that present externally encoded or scrambled data at the parallel interface. the embedded fifos may also be by- passed to create a reference-locked serial transmission link. for those systems requiring even greater fifo storage capa- bility, external fifos may be directly coupled to the cy7c924dx device through the parallel interface without ad- ditional glue-logic. the ttl parallel i/o interface may be configured as either a fifo (configurable for utopia emulation or for depth expan- sion through external fifos) or as a pipeline register extender. the fifo configurations are optimized for transport of time- independent (asynchronous) 8- or 10-bit character-oriented data across a link. a built-in self-test (bist) pattern generator and checker permits at-speed testing of the high-speed serial data paths in both the transmit and receive sections, and across the interconnecting links. hotlink devices are ideal for a variety of applications where parallel interfaces can be replaced with high-speed, point-to- point serial links. some applications include interconnecting workstations, backplanes, servers, mass storage, and video transmission equipment. figure 1. hotlink system connections deserializer framer 8b/10b decoder receive fifo tr a n s m i t fifo 8b/10b encoder serializer cy7c924dx receive data transmit data system host control status deserializer framer 8b/10b decoder receive fifo transmit fifo 8b/10b encoder serializer cy7c924dx receive data transmit data system host control status serial link serial link hotlink is a registered trademark of cypress semiconductor corporation. escon and ibm are registered trademarks of international business machines.
cy7c924dx 2 cy7c924dx transceiver logic block diagram ina inb outb outa routing matrix a/b* serial shifter bit clock bist lfsr 8b/10b encoder pipeline register mux mux elasticity buffer transmit fifo input register txdata tra ns m i t control tra ns m i t pll clock multiplier mux txclk refclk output register flags mode output register receive clock/data recovery bit clock deserializer framer clock divider bist lfsr 8b/10b decoder pipeline register byte-unpacker parity generation mux receive fifo address register mux receive control rxdata rxclk flags 3 mode rx status tx status cardet signal validation 13 tx status txempty* txhalf* txfull* 3 rxstatus lfi* rxempty* rxhalf* rxfull* 4 13 mode control control 9 11 parity checker byte-packer control am* txen* rxen* txstop* txrst* rxrst* rfen txbisten* rxbisten* mode rangesel spdsel address matching receive formatter tra ns m i t formatter state machine state machine rxmode[1:0] cursetb curseta loopback dlb[1:0] looptx control loopback control reset*[1:0] fifobyp* extfifo byte8/10* test* encbyp*
cy7c924dx 3 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature ................................. ? 65 c to +150 c ambient temperature with power applied ............................................. ? 55 c to +125 c supply voltage to ground potential ............... ? 0.5v to +6.5v dc voltage applied to outputs in high-z state ......................................... ? 0.5v to v dd +0.5v output current into ttl outputs (low) ...................... 30 ma dc input voltage ..................................... ? 0.5v to v dd +0.5v static discharge voltage ...............................................> 2001 v (per mil-std-883, method 3015) latch-up current ...........................................................> 200 ma pin configuration tqfp top view 1 3 2 92 91 90 84 85 87 86 88 89 83 82 81 76 78 77 79 80 93 94 95 96 97 98 99 100 59 60 61 67 66 64 65 63 62 68 69 70 75 73 74 72 71 spdsel rangesel rfen txfull* am* txhalf* rxsc/d* txclk vss vss vdd rxdata[1] txsoc/paren/txdata[11] rxrst* rxen* rxdata[0] txempty* vss txsvs/txdata[10] vdd txhalt*/txdata[9] rxdata[2] reset*[1] reset*[0] vdd 58 57 56 55 54 53 52 51 test* a/b* lfi* dlb[1] dlb[0] looptx vss rxclk rxfull* vss vdd vdd txen* txstop* txbisten* vss txrst* rxhalf* txsc/d* rxempty* txdata[0] rxsoc/rxdata[11] rxmode[1] rxmode[0] refclk 17 16 15 9 10 12 11 13 14 8 7 6 4 5 18 19 20 21 22 23 24 25 cardet vssa vdda curseta vdda vdda outa ? ina ? vssa vdda vdda vssa vssa vssa ina+ inb+ inb ? outb ? outb+ vdda vssa cursetb rxbisten* vssa outa+ 34 35 36 42 41 39 40 38 37 43 44 45 50 48 49 47 46 byte8/10* extfifo rxdata[3] rxdata[4] txint/txopin/txdata[8] rxdata[5] txdata[5] rxdata[6] rxdata[7] vss vss txdata[3] rxint/rxop/rxdata[8] txdata[6] txdata[7] txdata[4] vdd txdata[2] rxdata[9] txdata[1] rxrvs/rxdata[10] fifobyp* encbyp* vss vss 33 32 31 30 29 28 27 26 cy7c924dx operating range range ambient temperature v cc commercial 0 c to +70 c 5.0v 10% industrial ? 40 c to +85 c5.0v 10%
cy7c924dx 4 pin descriptions cy7c924dx hotlink transceiver pin # name i/o characteristics signal description transmit path signals 44, 42, 40, 36, 34, 32, 30, 22 txdata[7:0] ttl input, sampled on txclk or refclk , internal pull-up parallel transmit data input. bus width can be configured to accept either 8- or 10-bit characters. when the encoder is bypassed (encbyp* is low), txdata[7:0] functions as the least significant eight bits of the 10- or 12-bit pre-encoded transmit char- acter. 46 txint/ txopin/ txdata[8] ttl input, sampled on txclk or refclk , internal pull-up transmit interrupt input. this input is only interpreted if both the transmit fifo and encoder are en- abled. upon any state-change (0 1 or 1 0) in txint, a character is forced into the transmit encoder and shifter prior to accessing the next transmit fifo con- tents. this signal is routed around, not through, the transmit fifo. when txint transitions from 0 1, a c0.0 (k28.0) special code is sent. when txint transitions from 1 0, a c3.0 (k28.3) special code is sent. these spe- cial codes force a similar signal transition on the rxint output of an attached cy7c924dx hotlink transceiver. when the transmit fifo is bypassed (fifobyp* is low) and the encoder is enabled (encbyp* is high), this input is the odd parity input associated with the txdata[7:0], txsc/d*, and txsvs inputs when parity is enabled, and ignored otherwise. when the encoder is bypassed (encbyp* is low), txdata[8] functions as the 9th bit of the 10- or 12-bit pre-encoded transmit character. 54 txhalt*/ txdata[9] ttl input, sampled on txclk or refclk , internal pull-up transmit fifo halt immediate input. when txhalt* is asserted low, transmission of data is suspended and the hotlink transmits pad characters (k28.5). when txhalt* is deasserted high, normal data processing proceeds. when the encoder is bypassed (encbyp* is low), txdata[9] functions as the 10th bit of the 10- or 12-bit pre-encoded transmit character. txper ttl output, changes following txclk or refclk transmit parity error output. when the fifos are bypassed (fifobyp* is low) and the encoder is en- abled (encbyp* is high) this pin is an output and indicates that parity errors have been found in the txdata[7:0], txsc/d*, txsvs, and txopin inputs. 56 txsvs/ txdata[10] ttl input, sampled on txclk or refclk , internal pull-up transmit send violation symbol input. when the transmit fifo is enabled, this input is interpreted along with txsoc and txsc/d* (see ta b l e 2 for details). when the encoder is bypassed (encbyp* is low) and in 10-bit mode (byte8/10* is low), txdata[10] functions as the 11th bit of the 12-bit pre- encoded transmit character. 58 txsoc/ paren/ txdata[11] ttl input, sampled on txclk or refclk , internal pull-up transmit start of cell input. when the transmit fifo is enabled (fifobyp* is high), this input is used as a message frame delimiter to indicate the beginning of a data packet. it is interpreted along with txsvs and txsc/d* (see ta ble 2 for details). when the transmit fifo is bypassed (fifobyp* is low), this input is the parity enable input which enables odd parity checking of the txdata[7:0], txsc/d*, txsvs, and txopin inputs. when the encoder is bypassed (encbyp* is low) and in 10-bit mode (byte8/10* is low), txdata[11] functions as the 12th bit (msb) of the 12-bit pre-encoded transmit character.
cy7c924dx 5 20 txsc/d* ttl input, sampled on txclk or refclk internal pull-up transmit special character or data select input. when the transmit fifo is enabled, this input is interpreted along with txsvs and txsoc (see ta b l e 2 for details). when the encoder is bypassed (encbyp* is low) txsc/d* is ignored. 18 txen* ttl input, sampled on txclk or refclk internal pull-up transmit enable input. data enable for the txdata[11:0] data bus write operations. active high when configured for cascade timing, active low when configured for utopia timing. 9 txstop* ttl input, sampled on txclk , internal pull-up transmit stop on start_of_cell input. while the transmit fifo is enabled, this signal is used to prevent queued data characters from being serially transmitted. while txstop* is deasserted (high), data flows through the transmit fifo without interruption. when txstop* is asserted (low), data transfers continue until a txsoc bit is detected in the character stream, at which point data transmission ceases. if txstop* is momentarily deasserted and then reasserted, a single ? cell ? (de- limited by soc bits) is transmitted. stopped transfers and empty fifo condi- tions are padded with c5.0 (k28.5) characters. when the transmit fifo is bypassed (fifobyp* = low), txstop* has no function. this input can be left open or tied high. 68 txclk ttl clock input, internal pull-up transmit fifo clock. the input clock for the parallel interface when the transmit fifo is enabled. used to sample all transmit fifo related interface signals. 72 txfull* 3-state ttl output, changes following txclk or refclk transmit fifo full status flag. active low when configured for utopia timing, active high when configured for cascade timing. when the transmit fifo is enabled (fifobyp* is high), txfull* indicates a transmit fifo full condition. when txfull* is first asserted, the transmit fifo can accept a minimum of eight additional write cycles without loss of data. when the transmit fifo is bypassed (fifobyp* is low), with rangesel high or spdsel low, txfull* toggles at half the refclk rate to provide a character rate indication. data can be accepted when txfull* indicates a non-full condition. 70 txhalf* 3-state ttl output, changes following txclk or refclk transmit fifo half-full status flag. active low. when the transmit fifo is enabled, txhalf* is asserted low when the transmit fifo is half full (128 characters). txhalf* is only set to high-z state by the assertion of reset*[1:0] low. 60 txempty* 3-state ttl output, changes following txclk or refclk transmit fifo empty status flag. active low when configured for utopia timing, active high when configured for cascade timing. when the transmit fifo is enabled, txempty* is asserted either when no data has been loaded into the transmit fifo, or when the transmit fifo has been emptied by either a transmit fifo reset or by the normal transmission of the fifo contents. when txbisten* is asserted low, txempty* becomes the transmit bist- loop counter indicator (regardless of the logic state of fifobyp*). in this mode txempty* is asserted for one txclk period at the end of each transmitted bist sequence. when the transmit fifo is bypassed, txempty* is asserted to indicate that the transmitter can accept data. txempty* is also used as a bist progress indicator when txbisten* is asserted. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 6 16 txrst* ttl input, internal pull-up, sampled on txclk , internal pull-up transmit fifo reset. when txrst* is sampled asserted (low) for eight or more txclk cycles, a reset operation is started on the transmit fifo. this input is ignored when the transmit fifo is bypassed. 7 txbisten* ttl input, asynchronous, internal pull-up transmitter bist enable. when txbisten* is low, the transmitter generates a 511-character repeat- ing sequence, that can be used to validate link integrity. the transmitter returns to normal operation when txbisten* is high. all transmit fifo read oper- ations are suspended when bist is active. receive path signals 41, 43, 45, 47, 48, 53, 59, 61 rxdata[7:0] bidirectional ttl, changes following rxclk , or sampled by rxclk parallel data output and serial address register access. these outputs change following the rising edge of rxclk, when enabled to output data (the device is addressed by am* and selected by rxen*). the contents of this bus are interpreted differently based on the levels present on encbyp*, byte8/10*, rxsc/d*, and when accessing the serial address register. when the decoder is bypassed (encbyp* is low), rxdata[7:0] functions as the least significant eight bits of the 10- or 12-bit pre-encoded receive char- acter. 33 rxint/ rxop/ rxdata[8] bidirectional ttl, changes following rxclk , or sampled by rxclk receive interrupt output. when the receive fifo and decoder are enabled (fifobyp* and encbyp* are high) and a c0.0 (k28.0) special code is received, rxint is set high. when a c3.0 (k28.3) special code is received rxint is set low. these spe- cial codes are assumed to be generated in response to equivalent transitions on the txint input of an attached cy7c924dx hotlink transceiver. this signal is extracted prior to the receive fifo and (except for receive discard policy 0) the associated command codes are not considered ? data ? to be entered into the receive fifo and are discarded. when the receive fifo is bypassed and decoder is enabled (fifobyp* is low and encbyp* is high), this output contains the odd parity of the rxdata[7:0] and rxsc/d* outputs. when the decoder is bypassed (encbyp* is low), rxdata[8] functions as the 9th bit of the 10- or 12-bit undecoded receive character. 31 rxdata[9] bidirectional ttl, changes following rxclk , or sampled by rxclk receive data output. when the decoder is enabled in 10-bit mode (encbyp* is high and byte8/10* is low), this input is the 10th bit (msb) of the 10-bit decoded and unpacked data character. when the decoder is enabled and in 8-bit mode this input is ignored. when the decoder is bypassed (encbyp* is low), rxdata[9] functions as the 10th bit of the 10- or 12-bit undecoded receive character. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 7 29 rxrvs/ rxdata[10] bidirectional ttl, changes following rxclk , or sampled by rxclk , internal pull-up received violation symbol indicator. for normal data accesses this signal is used as an output. it is decoded in conjunction with rxsc/d* and rxsoc, per ta b l e 5 , to indicate the presence of specific special character codes in the received data stream. rxrvs is used to report bist pattern mismatches when rxbisten* is low. when accessing the serial address register, this signal is used as a ? read/write ? control input. rxrvs low allows the host system to write the serial address register (rxdata[9:0] and rxsc/d* are inputs). rxrvs high allows the host system to read the serial address register (rxdata[9:0] and rxsc/d* are outputs). when the decoder is bypassed (encbyp* is low) and in 10-bit mode (byte8/10* is low), rxdata[10] functions as the 11th bit of the 12-bit unde- coded receive character. when in 8-bit mode this output is unused and is driven low. 23 rxsoc/ rxdata[11] bidirectional ttl, changes following rxclk , or sampled by rxclk receive start of cell. active high. this output is decoded in conjunction with rxsc/d* and rxrvs, per ta ble 5 , to indicate the presence of specific special character codes in the received data stream. when the decoder is bypassed (encbyp* is low) and in 10-bit mode (byte8/10* is low), rxdata[11] functions as the 12th bit (msb) of the 12- bit undecoded receive character. when in 8-bit mode this output is unused and is driven low. 65 rxsc/d* bidirectional ttl, changes following rxclk , or sampled by rxclk received special character or data indicator. for normal data accesses this signal is used as an output. it is decoded in conjunction with rxsoc and rxrvs, per ta ble 5 , to indicate the presence of specific special character codes in the received data stream. when accessing the serial address register, this signal is used as an input to select the addressing mode. rxsc/d* high configures the serial address register for unicast address matching. rxsc/d* low configures the serial address register for multicast address matching. 69 rxen* ttl input, sampled on rxclk , internal pull-up receive enable. data enable for the rxdata[11:0] data bus write and read operations. active high when configured for cascade timing, active low when configured for utopia timing. used to select the parallel read interface of the device. also controls the read and write access to the serial address register. 8 rxclk bidirectional ttl clock, internal pull-up receive clock. when the receive fifo is enabled, this clock is the receive interface input clock and is used to control receive fifo read, reset, and serial register ac- cess operations. when the receive fifo is bypassed, this clock is output continuously at the character rate of the data being received (1/10th the serial bit-rate). 10 rxfull* 3-state ttl output, changes following rxclk receive fifo full flag. active low when configured for utopia timing, active high when configured for cascade timing. when the receive fifo is addressed, rxfull* is assert- ed when the receive fifo has room for eight or fewer writes. if the rxclk input is not continuous or the receive fifo is accessed at a rate slower than data is being received, rxfull* may indicate loss of data. when the receive fifo is bypassed, rxfull* and rxhalf* are deasserted to indicate that valid data may be present. rxfull* is also used as a bist progress indicator, and pulses asserted once every pass through the 511- character bist loop. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 8 19 rxhalf* ttl output, changes following rxclk receive fifo half-full flag. active low. when the receive fifo is enabled, this signal is asserted (low) when the receive fifo is half full (128 characters). when the receive fifo is by- passed, rxhalf* is deasserted (high). rxhalf* is forced to the high-z state only during a ? full-chip ? reset (i.e., while reset*[1:0] are low). 21 rxempty* 3-state ttl output, changes following rxclk receive fifo empty flag. active low when configured for utopia timing, active high when configured for cascade timing. when the receive fifo is enabled, rxempty* is assert- ed when no data remains in the receive fifo. any read operation occurring when rxempty is asserted results in no change in the fifo status, and the data from the last valid read remains on the rxdata bus. when the receive fifo is bypassed but the decoder is enabled, rxempty* is used as a valid data indicator. when deasserted it indicates that valid data (as selected by rxmode[1:0]) is present at the rxdata outputs. when as- serted it indicates that a c5.0 (k28.5) is present on the rxdata output bus. if both the receive fifo and the decoder are bypassed, rxempty* is deas- serted to indicate that all received characters are valid. 67 rxrst* ttl input, sampled on rxclk internal pull-up receive fifo reset. when the receive fifo is addressed and rxrst* is sampled while asserted (low) for eight or more rxclk cycles, a receive fifo reset is initiated. the rxrst* input is also asserted to access the serial address register. 73 rfen ttl input, asynchronous, internal pull-up reframe enable. used to control when the framer is allowed to adjust the character boundaries based on detection of one or more k28.5 characters in the data stream. when high, the framer is allowed to adjust the character boundaries relative to the received serial data stream. when low, the boundary is fixed. 77 rxbisten* ttl input, asynchronous, internal pull-up receiver bist enable. when active, the receiver is configured to perform a character-for-character match of the incoming data stream with a 511-character bist sequence. the result of character mismatches are indicated on rxrvs. completion of each 511-character bist loop is accompanied by an assertion pulse on the rxfull* flag. control signals 71 am* ttl input, sampled by txclk , rxclk , and refclk address match. active low. used as a qualifier for txen*, rxen*, txrst*, and rxrst*. also controls three-state enables for the txfull*, txempty*, rxfull*, and rxempty* signals. 6 looptx ttl input, asynchronous, internal pull-down serial-in to serial-out loop select. this input controls the loop-through function in which the serial data is re- covered by the clock/data recovery pll and is then retransmitted using the transmit pll as the bit-rate reference. it selects between the output of the transmit fifo and the output of the elasticity buffer as the input to the transmit encoder. when low, the transmit fifo is the source of data for transmission. when high, the elasticity buffer is the source of data for transmission. 12 refclk ttl input clock reference clock. this clock input is used as the timing reference for the transmit and receive plls. when the transmit fifo is bypassed, refclk is also used as the clock for the external transmit data interface. see table 4 for the relationships between refclk, spdsel, rangesel, and byte8/10*. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 9 75 spdsel static control input ttl levels normally wired high or low speed select. used to select one of two operating data rate ranges for the device. when the operating symbol rate is between 100 and 200 mbaud, spdsel must be high. when the operating symbol rate is between 50 and 100 mbaud, spdsel must be low (see ta ble 4 ). 74 rangesel static control input ttl levels normally wired high or low range select. selects the proper prescaler for the refclk input. see table 4 for the various relationships between refclk, spdsel, rangesel, and byte8/10*. when the transmit fifo is bypassed (fifobyp* is low), with rangesel high or spdsel low, txfull* toggles at half the refclk rate to provide a character rate indication, and to show when data can be accepted. 49 extfifo static control input ttl levels normally wired high or low external fifo select. extfifo modifies the active level of the rxen* and txen* inputs and the timing of the transmitter and receiver data buses. when not configured for external fifos (extfifo is low), txen* is assumed to be driven as a pipe- line register and rxen* is assumed to be driven by a controller for a pipeline register. in this mode the active data transition for the transmit data bus is within the same clock as the transmit interface is selected by txen*. when configured for external fifos (extfifo is high), txen is assumed to be driven by the empty flag of an attached cy7c42x5 fifo, and rxen is assumed to be driven by the almost full flag of an attached cy7c42x5 fifo. in this mode the active data transition for the transmit data bus is in the clock cycle following the clock edge where transmit interface is selected by txen*. extfifo also modifies the output state of the receive and transmit fifo flags. when configured for external fifos (extfifo is high), the full and empty fifo flags are active high (the half-full flag is always active low). when not configured for external fifos (extfifo is low), all of the fifo flags are active low. 28 fifobyp* static control input ttl levels normally wired high or low fifo bypass select. active low. when low, the transmit and receive fifos are bypassed. in this mode txclk is not used. instead all transmit data must be synchronous to refclk. transmit fifo status flags are synchronized to refclk. all received data is synchronous to the rxclk output. receive fifo status flags are synchro- nized to rxclk (the recovered receive pll character clock). when high, the transmit and receive fifos are enabled. in this mode all transmit fifo writes are synchronized to txclk , and all receive fifo reads are synchronous to the rxclk input. 27 encbyp* static control input ttl levels normally wired high or low encoder bypass select. active low. when low, both the encoder and decoder are bypassed. data is transmitted in nrz format, without encoding, lsb first. received data are presented as parallel characters to the interface without decoding. when high, data is passed through both the 8b/10b encoder in the transmit path and the decoder in the receive path. 24, 25 rxmode[1:0] static control input ttl levels normally wired high or low receive discard policy select. these inputs select between the four data handling and fill-character discard modes in the receiver. see table 6 . pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 10 50 byte8/10* static control input ttl levels normally wired high or low parallel data character size select. selects the input data character width. when byte8/10* is high, the device is in 8-bit mode. when byte8/10* is low, the part is in 10-bit mode. if the encoder is enabled (encbyp* is high), the data is encoded using the 8b/10b code rules found in table 10 and table 11 . when encbyp* is low, the part passes the 10 input bits (when byte8/10* is high) or 12 input bits (byte8/10* is low) directly to the serial stream without encoding or decoding. for affected pin groupings and function see table 1 and ta b l e 7 . 52, 51 reset*[1:0] ttl input, asynchronous global logic reset. these inputs are pulsed low for one or more refclk periods to reset the internal logic. they must be tied together or driven concurrently to ensure a valid reset. 1 test* ttl input, asynchronous. normally wired high factory test mode select. used to force the part into a diagnostic test mode used for factory ate test. this pin is tied high during normal operation. analog i/o and control 89, 90, 81, 82 outa outb pecl differential outputs differential serial data outputs. these pecl compatible outputs are capable of driving terminated transmis- sion lines or commercial fiber-optic transmitter modules. an unused output pair may be powered down by leaving the outputs uncon- nected and strapping the associated cursetx pin to v dd . 97 curseta analog input current-set resistor input for outa . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outa differential driver. 78 cursetb analog input current-set resistor input for outb . a precision resistor is connected between this input and a clean ground to set the output differential amplitude and currents for the outb differential driver. 94, 93, 86, 85 ina inb pecl compatible differential input differential serial data inputs. these inputs accept the serial data stream for deserialization and decoding. only one serial stream at a time may be fed to the receiver pll to extract the data content. this stream is selected using the a/b* input. these inputs may also be routed to the outb serial outputs using the dlb[1:0] inputs. 2 a/b* ttl input, asynchronous, internal pull-up receive data input selector. determines which internal or external serial bit-stream is passed to the receiv- er clock and data recovery circuit. see table 3 for details. 4,5 dlb[1:0] ttl input, asynchronous, internal pull-down loop-back select inputs. selects connections between serial inputs and outputs. controls diagnostic loop-back and serial loop-through functions. see table 3 for details. 100 cardet pecl input, asynchronous carrier detect input. used to allow an external device to signify a valid signal is being presented to the high speed pecl compatible input buffers, as is typical on an optical module. when cardet is deasserted low, the lfi * indicator asserts low signifying a link fault. this input can be tied to v dd for copper media applica- tions. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 11 3 lfi* ttl output, changes following rxclk link fault indication output. active low. lfi* changes synchronous with rxclk. this output is driven low when the serial link currently selected by a/b* is not suitable for data recovery. this can be caused by 1. serial data amplitude is below acceptable levels. 2. input transition density is not sufficient for pll clock recovery. 3. serial data stream is outside an acceptable frequency range of operation. 4. cardet is low. power 80, 87, 88, 95, 96, 98 v dda power for pecl i/o signals and internal analog circuits. 76, 79, 83, 84, 91, 92, 99 v ssa ground for pecl i/o signals and internal analog circuits. 14, 17, 35, 55, 62, 64 v dd power for cmos i/o signals and internal logic circuits. 11, 13, 15, 26, 37, 38, 39, 57, 63, 66 v ss ground for cmos i/o signals and internal logic circuits. pin descriptions (continued) cy7c924dx hotlink transceiver pin # name i/o characteristics signal description
cy7c924dx 12 cy7c924dx hotlink operation overview the cy7c924dx is designed to move parallel data across both short and long distances with minimal overhead or host system intervention. this is accomplished by converting the parallel characters into a serial bit-stream, transmitting these serial bits at high speed, and converting the received serial bits back into the original parallel data format. the cy7c924dx offers a large feature set, allowing it to be used in a wide range of host systems. some of the configura- tion options are: 8-bit or 10-bit character size user definable data packet or frame structure 2-octave data rate range asynchronous (fifoed) or synchronous data interface 8b/10b encoded or non-encoded (raw data) with or without parity check/generate embedded or bypassable fifo data storage multi-phy capability point-to-point, point-to-multipoint, or ring data-transport this flexibility allows the cy7c924dx to meet the data- transport needs of almost any system. transmit data path transmit data interface/transmit data fifo the transmit data interface to the host system is configurable as either an asynchronous buffered (fifoed) parallel interface or as a synchronous pipeline register. the bus itself can be configured for operation with 8-bit or 10-bit data. when configured for asynchronous operation (where the host- bus interface clock operates asynchronous to the serial char- acter and bit stream clocks), the host interface becomes that of a synchronous fifo clocked by txclk. in these configura- tions an internal 256-character transmit fifo is enabled. it allows the host interface to be written at any rate from dc to 50 mhz. when configured for synchronous operation, the transmit in- terface is clocked by refclk and operates synchronous to the internal character and bit-stream clocks. the input register must be written at the character rate, but refclk can operate at the character rate or at twice the character rate. both asynchronous and synchronous interface operations support two interface timing models: utopia and cascade. the utopia timing model is designed to match the active lev- els, bus timing, and signal sequencing called out in the atm forum utopia specification. the cascade timing model is designed to match a host bus that resembles a synchronous fifo. these timing models allow the cy7c924dx to directly couple to host systems, registers, state machines, fifos, etc., with minimal and in many cases no external glue logic. encoder data from the host interface or transmit fifo is next passed to an encoder block. the cy7c924dx contains an internal 8b/10b encoder that is used to improve the serial transport characteristics of the data. if parity checking is enabled, the characters are checked for valid odd parity. for those sys- tems that contain their own encoder or scrambler, this encoder may be bypassed. serializer/line driver the data from the encoder is passed to a serializer. this se- rializer operates at either 2.5, 5, or 10 times the rate of the refclk input (or 3, 6, or 12 times when in unencoded 10-bit mode). the serialized data is output from two pecl-compati- ble differential line drivers configured to drive transmission lines or optical modules. receive data path line receiver/deserializer/framer serial data is received at one of two pecl-compatible differ- ential line receivers. the data is passed to both a clock and data recovery pll (phase locked loop) and to a deserializ- er that converts serial data into parallel characters. the fram- er adjusts the boundaries of these characters to match those of the original transmitted characters. decoder the parallel characters are passed through a 10b/8b decoder and returned to their original form. if parity generation is en- abled, odd parity is added to the received characters at this point. for systems that make use of external decoding or de- scrambling, the decoder may be bypassed. receive data interface/receive data fifo data from the decoder is passed either to a receive fifo or is passed directly to the output register. the output register can be configured for operation with 8-bit or 10-bit data. when configured for an asynchronous buffered (fifoed) in- terface, the data is passed through a 256-character receive fifo that allows data to be read at any rate from dc to 50 mhz. when configured for synchronous operation (re- ceive fifo is bypassed) data is clocked out of the receive output register at the byte rate, up to 20 mhz. the receive interface is also configurable for both utopia and cascade timing models. cy7c924dx hotlink transceiver block diagram description transmit input/output register the transmit input register, shown in figure 2 , captures the data to be processed by the hotlink transmitter, and allows the input timing to be made compatible with asynchronous or synchronous host system buses. these buses can take the form of utopia compliant interfaces, external fifos, state machines, or other control structures. data present on the txdata[11:0] and txsc/d* inputs are captured at the rising edge of the selected sample clock. the transmit data bus bit- assignments vary depending on the data encoding, parity, and bus-width selected. these bus bit-assignments are shown in ta ble 1 , and list the functional names of these different signals. note that the function of several of these signals changes in different operating modes. the logical sense of the enable and fifo flag signals depends on the intended interface conven- tion and is set by the extfifo pin. the transmit interface supports both synchronous and asyn- chronous clocking modes, each supporting both utopia and
cy7c924dx 13 cascade timing models. the selection of the specific clocking mode is determined by the rangesel and spdsel inputs and the fifo bypass (fifobyp*) signal. synchronous interface synchronous interface clocking operates the entire transmit data path synchronous to refclk. it is enabled by connecting fifobyp* low to disable the internal fifos. asynchronous interface asynchronous interface clocking controls the writing of host bus data into the transmit fifo. it is enabled by setting fifobyp* high to enable the internal fifos. in these config- urations, all writes to the transmit input register, and associ- ated transfers to the transmit fifo, are controlled by txclk. the remainder of the transmit data path is clocked by refclk or synthesized derivatives of refclk. utopia timing model the utopia timing model allows multiple cy7c924dx trans- mitters to be addressed and accessed from a common host table 1. transmit input bus signal map transmit encoder mode [1] encoded 8-bit character stream pre-encoded 10-bit character stream encoded 10-bit character stream pre-encoded 12-bit character stream encbyp* high low high low byte8/10* high high low low txdata bus input bit txsc/d* txsc/d* txsc/d* txdata[0] txd[0] txd[0] [2] txd[0] txd[0] [2] txdata[1] txd[1] txd[1] txd[1] txd[1] txdata[2] txd[2] txd[2] txd[2] txd[2] txdata[3] txd[3] txd[3] txd[3] txd[3] txdata[4] txd[4] txd[4] txd[4] txd[4] txdata[5] txd[5] txd[5] txd[5] txd[5] txdata[6] txd[6] txd[6] txd[6] txd[6] txdata[7] txd[7] txd[7] txd[7] txd[7] txint/txopin/txdata[8] (fifobyp* = high) txint txd[8] txd[8] txd[8] txint/txopin/txdata[8] (fifobyp* = low) txopin txd[8] txd[8] txd[8] txhalt*/txper/txdata[9] (fifobyp* = high) txhalt* txd[9] txd[9] txd[9] txhalt*/txper/txdata[9] (fifobyp* = low) txper (output) txd[9] txd[9] txd[9] txsvs/txdata[10] txsvs txsvs txd[10] txsoc/txparen/txdata[11] (fifobyp* = high) txsoc txsoc txd[11] txsoc/txparen/txdata[11] (fifobyp* = low) txparen txd[11] notes: 1. all open cells are ignored. 2. first bit shifted out. others follow in numerical order creating an nrz pattern. transmit input register txen* txdata[11:0] 12 txclk refclk transmit fifo figure 2. transmit input register 14 to encoder block am* txsc/d*
cy7c924dx 14 bus, using the protocols defined in the atm forum utopia interface standards. it is enabled by setting extfifo low. in utopia timing, the txempty* and txfull* outputs and txen* input, are all active low signals. if the cy7c924dx is addressed by am*, it becomes ? selected ? when txen* is as- serted low. following selection, data is written into the trans- mit fifo on every clock cycle where txen* remains low. cascade timing model the cascade timing model is a variation of the utopia timing model. here the txempty* and txfull* outputs, and txen input, are all active high signals. cascade timing makes use of the same address and selection sequences as utopia tim- ing, but write data accesses use a delayed write. this delayed write is necessary to allow direct coupling to external fifos, or to state machines that initiate a write operation one clock cycle before the data is available on the bus. cascade timing is enabled by setting extfifo high. when used for fifo depth expansion, cascade timing allows the size of the internal transmit fifo to be expanded to an almost unlimited depth. it allows a cy7c42x5 series synchro- nous fifo to be attached to the transmit interface without any extra logic, as shown in figure 3 . transmit fifo the transmit fifo is used to buffer data captured in the input register for later processing and transmission. this fifo is sized to hold 256 14-bit characters. when the transmit fifo is enabled, and a transmit fifo write is enabled (the device is selected and txen* is sampled asserted), data and com- mand are captured in the transmit input register and stored into the transmit fifo. all transmit fifo write operations are clocked by txclk. the transmit fifo presents full, half-full, and empty fifo flags. these flags are provided synchronous to txclk. when the transmit fifo is enabled, it allows operation with a moore- type external controlling state machine. when configured for cascade timing, the timing and active levels of these signals are also designed to support direct expansion to cypress cy7c42x5 synchronous fifos. regardless of bus width (8- or 10-bit characters) the transmit fifo can be clocked at any rate from dc to 50 mhz. this gives the transmit fifo a maximum bandwidth of 50 million charac- ters per second. since the serial outputs can only move 20 million characters per second at their fastest operating rate, there is ample time to service multiple cy7c924dx hotlinks with a single controller. the read port of the transmit fifo is connected to a logic block that performs data formatting and validation. all data read operations from the transmit fifo are controlled by a transmit control state machine that operates synchronous to refclk. transmit formatter and validation the transmit formatter and validation logic performs three pri- mary functions: parity checking data format control byte-packing in addition to these logic functions, this block also controls the timing for the transfer of data from the transmit input register, transmit fifo, or elasticity buffer. parity checking parity checking is enabled in 8-bit encoded mode when the internal fifos are disabled (fifobyp* is low) and paren (txsoc) is high. odd parity is supported, which requires at least one bit of the data bus to always be a logic-1. the eight data bits (txdata[7:0]), txsc/d*, txsvs, and txopin (txdata[8]) are covered by the parity checking hardware. if a parity error is detected in a character, that character is not transmitted, but is replaced with the c0.7 exception character (see special character codes in table 11 ). this prevents bad data from knowingly being transmitted and informs the receiv- er that an error was detected in the source data stream. parity errors are reported to the transmit interface through the txper output. this output pulses high for one refclk pe- riod, one or more cycles after the cycle where the parity error was detected. transmit data formatting the cy7c924dx supports a number of protocol enhance- ments over a raw physical-layer device. these enhancements are made possible in part through the use of the transmit and receive fifos. these fifos allow the cy7c924dx to man- age the data stream to a much greater extent than was possi- ble before. in addition to the standard 8b/10b encoding used to improve serial data transmission, the cy7c924dx also sup- ports: marking of packet or cell boundaries using txsoc an expanded command set ability to address and route packets or frames to specific receivers all three of these capabilities are supported for both 8- and 10- bit encoded character sizes, and are made possible through use of the txsoc bit. this bit is interpreted, along with txsc/d* and txsvs, in those modes where both the transmit fifo and the encoder are enabled. all three bits determine how the data associated with them is processed for transmis- sion. these operations are listed in table 2 . the entries in table 2 , where txsoc is low generate the same characters in the serial data stream as a standard cy7b923 hotlink transmitter, which uses the ansi standard 8b/10b character set. the data, command, and exception character encodings are listed in the data and special char- figure 3. external fifo depth expansion of the cy7c924dx transmit data path ff* wen* d txclk ff* wen* d wclk ef* ren* q rclk txen txfull txdata txclk txsc/d* cy7c42x5 fifo cy7c924dx extfifo ? 1 ?
cy7c924dx 15 acter code tables ( tables 10 and 11 ) found near the end of this data sheet. when the txsoc bit (as read from the transmit fifo) is high, an extra character is inserted into the data stream. this extra character is always a special character code (see ta b l e 11 ) that is used to inform the remote receiver that the immedi- ately following character should be interpreted differently from its normal meaning. the associated character present on txdata[x:0] is always encoded as a data character. the 100b combination (txsoc = 1, txsc/d* = 0, and txsvs = 0) is used as a marker for the start of a cell, frame, or packet of data being sent across the interface. when a char- acter is read from the transmit fifo with this combination of bits set, a c8.0 special character code is sent to the encoder prior to sending the associated data character. the 101b character format has the same function as the 001b and 011b normal data modes. it instructs the encoder to dis- card the associated data character and to replace it with a c0.7 exception character. the 110b character format is used to expand the command space beyond that available with the default 8b/10b code. the 8b/10b code normally supports a data space of 256 data char- acters, and a command (non-data) space of twelve command characters (c0.0 ? c11.0 in table 11 ). for those data links where this is not sufficient, the 110b format can be used to mark the associated data as an extended command. this ex- pands the command space to 256 commands (in addition to some of the present twelve). when a character is read from the transmit fifo with these bits set, a c9.0 special charac- ter code is sent to the encoder prior to sending the data char- acter. the 111b character format is used to send a serial addresses to attached receivers. these serial addresses allow a host to direct (the following) data to a specific destination or destina- tions, when the cy7c924dx devices are connected in a ring or bus topology. the serial address marker may also be used to send packet identification fields, sequence numbers, or other high-level routing information for those point-to-point connections that do not require physical address capabilities, however, the report- ing of the address field contents may be affected by the present receiver discard policy. this marking or tagging capa- bility can be performed with the 100b or 110b character for- mats without concern for receiver discard policy. when a character is read from the transmit fifo with these bits set, a c10.0 special character is sent to the encoder prior to sending the associated data character. byte-packer the byte-packer is a logical construct, used to control the effi- cient segmentation of 10-bit source data into 8-bit characters. this conversion allows these characters to be transported us- ing 8b/10b encoding, with the same encoding overhead (20%) as when sending 8-bit characters. because the serializer con- tinues to operate using 10-bit transmission characters, this en- coding mode can only operate with the transmit fifo enabled. the byte-packer operates by taking pieces of one or more 10- bit characters, combining them into 8-bit groups, and passing these groups to the 8b/10b encoder. it takes exactly five 8-bit characters to transport four 10-bit characters. the allocation is performed, as shown in figure 4 , where the low-order eight bits of the first 10-bit character (a[7:0]) are passed to the en- coder on the first clock cycle. during the second clock cycle the remaining two bits of the first character are combined with the lower six bits of the second 10-bit character (b[5:0]+a[9:8]). in the third clock cycle the remaining four bits of the second 10-bit character are combined with the lower four bits of the third 10-bit character (c[3:0]+b[9:6]). in the fourth clock cycle the remaining six bits of the third 10-bit character are combined with the lower two bits of the fourth 10-bit char- acter (d[1:0]+c[9:4]). in the fifth clock cycle the remaining eight bits of the fourth 10-bit character are passed to the en- coder (d[9:2]). this process repeats for additional data characters present in the fifo. if at any time the transmit fifo is emptied, and a portion of a 10-bit character has not yet been transmitted, the remaining bits of the 8-bit character are filled with dummy bits before that character is passed to the encoder. the 8-bit char- acter containing these dummy bits is immediately followed by table 2. transmit data formatting txsoc txsc/d* txsvs data format operation 0 0 0 normal data encode 0 0 1 replace character with c0.7 exception 0 1 0 normal command encode 0 1 1 replace character with c0.7 exception 1 0 0 send start of cell marker (c8.0) + data character 1 0 1 replace character with c0.7 exception 1 1 0 send extended command marker (c9.0) + data character 1 1 1 send serial address marker (c10.0) + data character
cy7c924dx 16 a c5.0 (k28.5) fill character, which resets the sequencer boundaries to the first character position. encoder block the encoder logic block performs two primary functions: en- coding the data for serial transmission and generating bist (built-in self test) patterns to allow at-speed link and device testing. bist lfsr the encoder logic block operates on data stored in a register. this register accepts information directly from the transmit fifo, the transmit input register, the 10/8 byte-packer, or from the transmit control state machine when it inserts spe- cial characters into the data stream. this same register is converted into a linear feedback shift register (lfsr) when the built-in self-test (bist) pattern generator is enabled (txbisten* is low). when enabled, this lfsr generates a 511-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable but pseudo- random sequence that can be matched to an identical lfsr in the receiver. the specific patterns generated are described in detail in the cypress application note ? hotlink built-in self-test. ? the se- quence generated by the cy7c924dx is identical to that in the cy7b923 and cy7c929, allowing interoperable systems to be built when used at compatible serial signaling rates. encoder the data passed through the transmit fifo and formatter, or as received directly from the transmit input register, is seldom in a form suitable for transmission across a serial link. the characters must usually be processed or transformed to guar- antee: a minimum transition density (to allow the serial receiver pll to extract a clock from the data stream) a dc-balance in the signaling (to prevent baseline wander) run-length limits in the serial data (to limit the bandwidth of the link) some way to allow the remote receiver to determine the correct character boundaries (framing). the cy7c924dx contains an integrated 8b/10b encoder that accepts 8-bit data characters and converts these into 10-bit transmission characters that have been optimized for transport on serial communications links. the 8b/10b encoder can be bypassed for those system that operate with external 8b/10b encoders, or use alternate forms of encoding or scrambling to ensure good transmission characteristics. the operation of the 8b/10b encoding algorithm is described in detail later in this data sheet, and the complete encoding tables are listed in ta- bles 10 and 11 . when the encoder is enabled, the transmit data characters (as passed through the transmit fifo and formatter) are converted to either a 10-bit data symbol or a 10-bit special character, depending upon the state of the txsc/d* input. if txsc/d* is high, the data inputs represent a special character code and are encoded using the special character encoding rules in table 11 . if txsc/d* is low, the data inputs are encoded using the data character encod- ing in table 10 . when operated without parity checking, the msb of each char- acter is used to override the contents of the remaining bits in the character. if this bit (txsvs) is high, the respective char- acter is replaced with an svs (c0.7) character. this can be used to check error handling system-logic in the receiver control- ler or for proprietary applications. the 8b/10b encoder is standards compliant with ansi/ncits asc x3.230-1994 (fibre channel), ieee 802.3z (gigabit ethernet), the ibm escon and ficon channels, and atm forum standards for data transport. the 8b/10b coding function of the encoder can be bypassed for systems that include an external coder or scrambler func- tion as part of the controller or host system. this is performed by setting encbyp* low. with the encoder bypassed, each 10-bit character (as captured in the transmit input register) is passed directly to the transmit shifter (or transmit fifo) with- out modification. transmit shifter the transmit shifter accepts 10-bit parallel data from the en- coder block once each character time, and shifts it out the serial interface output buffers using a pll-multiplied bit-clock. this bit-clock runs at 2.5, 5, or 10 times the refclk rate (3, 6, or 12 times when byte8/10* is low) as selected by rangesel and spdsel (see ta b l e 4 ). timing for the parallel transfer is controlled by the counter and dividers in the clock multiplier pll and is not affected by signal levels or timing at the input pins. bits in each character are shifted out lsb first, as required by ansi and ieee standards for 8b/10b coded serial data streams. routing matrix the routing matrix is a set of precision multiplexors that allow various combinations of transmit shifter, buffered ina or inb serial line receiver inputs, or a reclocked serial line re- ceiver input to be transmitted from the outb serial data out- puts. the signal routing for the transmit serial outputs is con- trolled primarily by the dlb[1:0] inputs as listed in table 3 . figure 4. byte-packer 10-to-8 character mapping aaaaaaaa 76543210 bbbbbbaa 54321098 dddddddd 98765432 ddcccccc 10987654 ccccbbbb 32109876 first character last character sent sent source 10-bit character stream dddddddddd cccccccccc bbbbbbbbbb aaaaaaaaaa 9876543210 9876543210 9876543210 9876543210
cy7c924dx 17 serial line drivers the serial interface pecl output drivers (ecl referenced to +5v) are the transmission line drivers for the serial media. outa receives its data directly from the transmit shifter, while outb receives its data from the routing matrix. these two outputs (outa and outb ) are capable of direct connection to +5v optical modules, and can also directly drive dc- or ac- coupled transmission lines. the pecl-compatible output drivers can be viewed as pro- grammable current sources. the output voltage is determined by the output current and the load impedance z load . the de- sired output voltage swing is therefore controlled by the cur- rent-set resistor r curset associated with that driver. different r curset values are required for different line impedance/am- plitude combinations. the output swing is designed to center around v dd ? 1.33v. each output must be externally biased to v dd ? 1.33v. this differential output-swing can be specified two ways: either as a peak-to-peak voltage into a single-end load, or as an ab- solute differential voltage into a differential load. when specified into a single-ended load (one of the outputs switching into a load), the single output will both source and sink current as it changes between its high and low levels. the voltage difference between this high level and low level determine the peak-to-peak signal-swing of the output. this amplitude relationship is controlled by the load impedance on the driver, and by the resistance of the r curset resistor for that driver, as listed in eq. 1 eq. 1 in eq. 1 , v opp is the difference in voltage levels at one output of the differential driver when that output is driving high and low, z load is that load seen by the one output when it is sourcing and sinking current. with a known load impedance and a desired signal swing, it is possible to calculate the value of the associated curseta or cursetb resistor that sets this current. unused differential output drivers should be left open, and can reduce their power dissipation by connecting their respective cursetx input to v dd . transmit pll clock multiplier the transmit pll clock multiplier accepts an external clock at the refclk input, and multiples that clock by 2.5, 5, or 10 (3, 6, or 12 when byte8/10* is low and the encoder is disabled) to generate a bit-rate clock for use by the transmit shifter. it also provides a character-rate clock used by the transmit con- troller state machine. the clock multiplier pll can accept a refclk input between 8 mhz and 40 mhz, however, this clock range is limited by the operation mode of the cy7c924dx as selected by the spdsel and rangesel inputs, and to a limited extent, by the byte8/10* and fifobyp* signals. the operating serial signalling rate and allowable range of refclk frequencies is listed in ta b l e 4 . transmit control state machine the transmit control state machine responds to multiple in- puts to control the data stream passed to the encoder. it oper- ates in response to: the state of the fifobyp* and looptx inputs the presence of data in the transmit fifo the contents of the transmit fifo the contents of the elasticity buffer the state of the transmitter bist enable (txbisten*) the state of external halt signals (txhalt* and txstop*) table 3. transmit data routing matrix dlb[1] dlb[0] data connections 00 01 10 11 ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b* ina inb outb outa transmit shifter receive pll a/b* table 4. speed select and range select settings spdsel rangesel serial data rate (mbaud) refclk [4] frequency (mhz) low low 50 ? 100 10 ? 20 low high [3] 50 ? 100 20 ? 40 high low 100 ? 200 10 ? 20 high high 100 ? 200 20 ? 40 notes: 3. when spdsel is low and the fifos are bypassed (fifobyp* is low), the rangesel input is ignored and is internally mapped to the low setting. 4. when configured for 12-bit pre-encoded data (byte8/10* and encbyp* are both low) the allowable refclk ranges are 8.33to 16.67 mhz and 16.67 to 33.33 mhz. r curset 180 z load v opp --------------------------------- - =
cy7c924dx 18 these signals are used by the transmit control state machine to control the data formatter, read access to the transmit fifo and elasticity buffer, the byte-packer, and bist. they deter- mine the content of the characters passed to the encoder and transmit shifter. when the transmit fifo is bypassed, the transmit control state machine operates synchronous to refclk. in this mode, data from the txdata bus (or other source) is passed directly from the input register to the pipeline register. if no data is enabled into the input register (txen* is deasserted or txfull* is asserted) then the transmit control state machine presents a c5.0 special character code to the encoder to maintain link synchronization. if both the encoder and transmit fifo are bypassed and no data is enabled into the input register, the transmit control state machine injects an alternating disparity sequence of pre- encoded (10-bit) forms of the c5.0 characters. this also oc- curs if the encoder is bypassed, the transmit fifo is enabled, and the transmit fifo is empty. however, since disparity tracking is part of the encoder, the transmitted c5.0 characters may generate a running disparity error at the remote receiver. if the attached receiver has its decoder enabled, these char- acters may be reported as a normal c5.0, or as a c1.7 or c2.7 (k28.5 with incorrect running disparity). external control of data flow the transmit control state machine supports three different types of external control: txstop* txhalt* txint these control signal inputs are only interpreted when the transmit fifo is enabled. they effect the transmission of data by bringing external signals to the state machine without send- ing the signals through the transmit fifo. txstop* is used to stop transmission of the next packet or cell of data in the transmit fifo. when asserted (low) the transmit control state machine continues to read and process characters in the transmit fifo until a location is read with the txsoc bit set. once a txsoc is detected, the state machine sends out c5.0 fill characters until txstop* is deasserted (high) for one or more character times. when txstop* is sampled deasserted it allows the next character with txsoc set to be read from the transmit fifo and passed to the en- coder. when txstop* is used to control the flow of data, it is assert- ed (low) most of the time. to allow a cell or frame to pass, it only needs to be deasserted (high) for one txclk cycle (as- suming the transmit controller is at a cell boundary). once the first character of the cell is transmitted the remainder of that cell is also processed. this allows the host system to control the transmission of data across the interface on a cell-by-cell or packet-by-packet basis. txhalt* (txdata[9]) is an immediate form of txstop*. in- stead of continuing to transmit data until a txsoc is found, the assertion of txhalt* causes character processing to stop at the next fifo character location. no additional data is read from the transmit fifo until txhalt* is deasserted (high). note: if the encoder is bypassed, txdata[9] is a data input and not txhalt*. since in this mode the interface does not interpret the txsoc bit, the txstop* signal as- sumes the same functionality as txhalt*. txint is used to send one of two interrupt characters from the local transmitter to a remote receiver. while it also bypasses the transmit fifo, it does not stop data transmission (at least not directly). the transmit control state machine responds to transitions on the txint input. when txint transitions from 0 1, a c0.0 (k28.0) special character code is sent. when txint transi- tions from 1 0, a c3.0 (k28.3) special character code is sent. the reception of these characters generates an equiva- lent action on the attached receiver ? s rxint status output. the combination of rxhalf*, txint, rxint, and txhalt* may be used to prevent a remote fifo overflow, which would result in lost data. this back-pressure mechanism can signifi- cantly improve data integrity in systems that cannot guarantee the full bandwidth of the host system at all times. elasticity buffer a short (8-character) fifo is contained between the receive and transmit paths. this fifo is used to separate the time domains of the received serial data stream and the outbound transmit data stream. this permits retransmission of received data without worry of jitter gain or jitter transfer. this allows error-free transmission of the same data, when configured in daisy-chain or ring configurations, to an unlimited number of destinations. this elasticity buffer is enabled when the looptx input is asserted high. this directs the receiver to place all non-c5.0 (k28.5) characters into the elasticity buffer. looptx also di- rects the transmit control state machine to read data from the elasticity buffer instead of from the transmit fifo. while retransmitting data from the elasticity buffer, the trans- mit fifo is available for pre-loading of data to be transmitted. once looptx is deasserted (low), normal data transmis- sion from the transmit fifo resumes. this looptx capability is only possible when sending 8-bit encoded data streams. it cannot be used with byte-packed or non-encoded data streams, and requires that the transmit and receive fifos are enabled. it also requires that the receiver be configured to process embedded commands (receiver dis- card policy cannot be 0). serial line receivers two differential line receivers, ina and inb , are available for accepting serial data streams, with the active input selected using the a/b* input. the dlb[1:0] inputs allow the transmit serial- izer output to be selected as a third input serial stream, but this path is generally used only for diagnostic purposes. the serial line re- ceiver inputs are all differential, and will accommodate wire intercon- nect with filtering losses or transmission line attenuation greater than 9 db (v dif > 200 mv, or 400 mv peak-to-peak differential) or can be directly connected to +5v fiber-optic interface modules (any ecl logic family, not limited to ecl 100k). the common-mode tol- erance of these line receivers accommodates a wide range of signal termination voltages. as can be seen in ta b l e 3 , these inputs are configured to allow single-pin control for most applications. for those systems requiring selection of only ina or inb , the dlb[1:0] signals can be tied low, and the a/b selection can be performed using only a/b*. for those systems requiring only a single input and a local loopback, the
cy7c924dx 19 a/b* can be tied high or low, dlb[1] signal can be tied low and dlb[0] can be used for loopback control. the level-restored (10b) and reclocked (11b) settings make use of one of the transmit data outputs. when configured for level-restored or reclocked data, the selected input is retrans- mitted on outb . the level-restored connection simply buff- ers the input signal allowing a ? bus-like ? connection to be con- structed without concern for multi-drop pecl signal layout issues. the reclocked connection buffers a pll-filtered copy of the selected input data stream. this removes most of the high- frequency jitter that accumulates on a signal when sent over long transmission lines. unlike data retransmitted from the elasticity buffer, the output data stream is clocked by a recov- ered clock, not by a derivative of the local reflck input. this allows a data source to provide data to multiple recipients, but can suffer from jitter peaking when communicated through several plls. the reclocked connection may be required when sending non-8b/10b coded data streams, or data streams that cannot tolerate the data forwarding policies of the elasticity buffer. this reclocked output stream may also be beneficial in sys- tems requiring very low latency. the internal data delays for a reclocked serial stream are a small number of bits, while data sent through the elasticity buffer incurs a delay of a small num- ber of characters. signal detect the selected line receiver (that routed to the clock and data recovery pll) is simultaneously monitored for: analog amplitude (>400 mv pk-pk) transition density received data stream outside normal frequency range ( 400 ppm) and carrier detected. all of these conditions must be valid for the signal detect block to indicate a valid signal is present. this status is presented on the lfi* (link fault indicator) output, which changes synchro- nous to rxclk. while link status is monitored internally at all times, it is necessary to have transitions on rxclk to allow this signal to change externally. clock/data recovery the extraction of a bit-rate clock and recovery of data bits from the received serial stream is performed within the clock/data recovery (cdr) block. the clock extraction function is per- formed by a high-performance embedded phase-locked loop (pll) that tracks the frequency of the incoming bit stream and aligns the phase of its internal bit-rate clock to the transitions in the serial data stream. the cdr makes use of the clock present at the refclk input. it is used to ensure that the vco (within the cdr) is operating at the correct frequency (rather than some harmonic of the bit rate), to improve pll acquisition time, and to limit unlocked frequency excursions of the cdr vco when no data is present at the serial inputs. regardless of the type of signal present, the cdr will attempt to recover a data stream from it. if the frequency of the recov- ered data stream is outside the limits for the range controls, the cdr pll will track refclk instead of the data stream. when the frequency of the selected data stream returns to a valid frequency, the cdr pll is allowed to track the received data stream. the frequency of refclk is required to be within 400 ppm of the frequency of the clock that drives the refclk signal at the remote transmitter to ensure a lock to the incom- ing data stream. for systems using multiple or redundant connections, the lfi* output can be used to select an alternate data stream. when an lfi* indication is detected, external logic can toggle selec- tion of the ina and inb inputs through the a/b* input. when a port switch takes place, it is necessary for the pll to re- acquire the new serial stream and frame to the incoming char- acters. clock divider this block contains the clock division logic, used to transfer the data from the deserializer/framer to the decoder once every character (once every ten or twelve bits) clock. this counter is free running and generates outputs at the bit-rate divided by 10 (12 when the byte8/10* and encbyp* are low). when the receive fifo is bypassed, one of these generated clocks is driven out the rxclk pin. deserializer/framer the cdr circuit extracts bits from the serial data stream and clocks these bits into the shifter/framer at the bit-clock rate. when enabled, the framer examines the data stream looking for c5.0 (k28.5) characters at all possible bit positions. the location of this character in the data stream is used to deter- mine the character boundaries of all following characters. the framer operates in one of three different modes, as select- ed by the rfen input. when rfen is first asserted (high), the framer is allowed to reset the internal character boundaries on any detected c5.0 character. once rfen has been high for greater than approximately 2000 character clock cycles, the multi-byte framer is enabled. this requires two c5.0 characters within a span of five char- acters, with both c5.0 characters located on identical 10-bit character boundary locations, before the framer is allowed to reset the internal character boundary. if rfen is low, the framer is disabled and no changes are made to character boundaries. the framer in the cy7c924dx operates by shifting the internal character position to align with the character clock. this en- sures that the recovered clock does not contain any significant phase changes/hops during normal operation or framing, and allows the recovered clock to be replicated and distributed to other circuits using pll-based logic elements. decoder block the decoder logic block performs two primary functions: de- coding the received transmission characters back into data and special character codes, and comparing generated bist patterns with received characters to permit at-speed link and device testing. 10b/8b decoder the framed parallel output of the deserializer is passed to the 10b/8b decoder where, if the decoder is enabled, it is trans- formed from a 10-bit transmission character back to the origi- nal data and special character codes. this block uses the standard decoder patterns in tables 10 and 11 of this data sheet. data patterns are indicated by a low on rxsc/d*, and
cy7c924dx 20 special character codes are indicated by a high. invalid patterns or disparity errors are signaled as errors by a high on rxrvs, and by specific special character codes. if the decoder is bypassed and byte8/10* is high, the ten (10) data bits of each transmission character are passed un- changed from the framer to the pipeline register. when the decoder is bypassed and byte8/10* is low, the twelve (12) data bits of each transmission character are passed unchanged from the framer to the pipeline register. bist lfsr the output register of the decoder block is normally used to accumulate received characters for delivery to the receive formatter block. when configured for bist mode (rxbisten* is low), this register becomes a signature pat- tern generator and checker by logically converting to a linear feedback shift register (lfsr). when enabled, this lfsr generates a 511-character sequence that includes all data and special character codes, including the explicit violation symbols. this provides a predictable but pseudo-random se- quence that can be matched to an identical lfsr in the trans- mitter. when synchronized with the received data stream, it checks each character in the decoder with each character generated by the lfsr and indicates compare errors at the rxrvs output of the receive output register. the lfsr is initialized by the bist hardware to the bist loop start code of d0.0 (d0.0 is sent only once per bist loop). once the start of the bist loop has been detected by the receiver, rxrvs is asserted for pattern mismatches between the re- ceived characters and the internally generated character se- quence. code rule violations or running disparity errors that occur as part of the bist loop do not cause an error indication. rxfull* pulses asserted for one rxclk cycle per bist loop and can be used to check test pattern progress. the specific patterns checked by the receiver are described in detail in the cypress application note ? hotlink built-in self- te s t . ? the sequence compared by the cy7c924dx is identical to that in the cy7b933, allowing interoperable systems to be built when used at compatible serial signaling rates. if a large number of errors are detected, the receive bist state machine aborts the compare operations and resets the lfsr to the d0.0 state to look for the start of the bist sequence again. receive formatter the receive formatter performs four primary functions: data formatting address matching byte-unpacking parity generation receive data formatting the protocol enhancements of the transmit path are mirrored in the receive path logic. the majority of these enhancements require that the receive fifo be enabled to allow the cy7c924dx to manage the data stream. in addition to the standard 10b/8b decoding used for character reception and recovery, the cy7c924dx also supports: marking of packet or cell boundaries using rxsoc an expanded control/command character set ability to accept or discard data based on an embedded address the ability to filter receive data of non-essential information all of these capab ilities are supported for both 8- and 10-bit character sizes, and are made possible through use of the rxsoc bit. rxsoc is generated upon reception of the c8.0, c9.0, or c10.0 special character codes, in those modes where both the receive fifo and the decoder are enabled. the entries in ta ble 5 show how the rxsoc, rxsc/d*, and rxrvs bits are formatted to indicate the reception of specific characters and character combinations. normal data and special character code characters are indicated by rxsoc being low (0). this allows the standard special characters codes to also be reported and output. individual character errors that are not part of one of the sup- ported sequences (start of cell, extended command, or se- rial address) are marked by the 011b (rxsoc = 0, rxsc/d* = 1, and rxrvs = 1) decode. anytime rxsoc is reported high (1) at least one of the c8.0, c9.0, or c10.0 characters was received as a valid character. if the immediately following character is a valid data character, then the corresponding combination of rxsoc, rxsc/d*, and rxrvs indicate the type of information received. if the immediately following character is a special character code of any type (even a c5.0), then a 101b is posted to indicate an illegal sequence was received. an illegal sequence can be caused by a remote transmitter sending incorrect information, or by receiving data corrupted during transmission. when such an error is detected, the 101b status bits are posted and the associated data field is set to the special character code that was received without error (c8.0, c9.0, or c10.0 reported as d8.0, d9.0, or d10.0 along with the 101b status). this information is provided to assist in debugging link or protocol faults. the 100b indication is used to mark the associated data char- acter as the first character of a new frame, packet, cell, or other data construct used by the system. the data characters and special character codes that follow this marker are written to table 5. receive data formatting rxsoc rxsc/d* rxrvs data format indication 0 0 0 normal data character 001reserved 0 1 0 normal command character 0 1 1 received c0.7 exception character or other character exception (as listed in table 11 ) 1 0 0 received start of cell marker (c8.0) + data character 1 0 1 received illegal sequence 1 1 0 received extended command marker (c9.0) + data character (interpreted as a command) 1 1 1 received serial address marker (c10.0) + data character (interpreted as an address)
cy7c924dx 21 the receive fifo (if the present address matching require- ments are satisfied). the 110b indication is used to mark the associated data char- acter as the first character of an extended command. in reality there is no limit to the number of immediately following data characters that can be considered part of this command. the most common interpretation is based on the configured bus width, such that single-character configurations support the associated character as the extended command, providing up to 256 extended commands for 8-bit data and 1024 for 10-bit byte-packed data. this marker is treated internally the same as the 100b start of cell indication, which allows it to be used to mark the boundary of any user-specific information. as a boundary or cell marker, the immediately following data can be a data field, a header, a stream identifier, a transaction number, a packet length indica- tor, or any of a number of pieces of information connected to a data transfer. note: in reality, the 100b and 110b indicators can be used interchangeably; i.e., the 100b indication can be used to mark extended commands while the 110b indication can be used to mark the start of cells. the 111b indication is used to mark the start of a serial ad- dress field. unlike the start of cell and extended command markers, which have no specific data-field length associated with them, the associated serial address is always comprised of the immediately following single data character, and sup- ports a fixed 8-bit or 10-bit address field format in 8-bit or 10- bit byte-packed data formats. when this serial address is received it may be passed to the receive fifo or discarded (see ta b l e 6 ) . address matching for those modes where address matching is enabled, the cy7c924dx ? s ability to accept or discard data can be con- trolled by the remote transmitter. this is often useful in config- urations with one or more data sources and multiple data des- tinations. each cy7c924dx contains an 8-bit or 10-bit serial address register that is compared with the first data character received following a serial address marker (c10.0). this character con- stitutes an address, which can be configured for one of two modes for address matching. the first mode is used for multi- cast addresses, where a bit-wise and is performed on each bit of the address character received, with the contents of each of the bits in the serial address register. if any of the same bit locations in the register and the received data are both set to ? 1 ? , a multicast address match is declared and the following data and special character codes are interpreted and passed to the receive fifo. if the multicast address field is ever received as all 1s (ffh or 3ffh), the receiver always accepts the data. this all 1s setting is the broadcast address and is used to send data to all re- ceivers. this all 1s setting also has special meaning when written to the serial address register. when the multicast address field is written to an all 1s (ffh or 3ffh) state, the receiver operates in promiscuous mode, and receives all data, regardless of the contents of any serial address commands received. this is also the default or power-up state of the serial address reg- ister. the second mode of operation for address matching is when the serial address register contains a unique device address, and is compared with the character received following the c10.0 serial address marker. this unicast address requires an exact match between all 8 or 10 bits to declare a match found and allow the following data to pass. when the elasticity buffer is enabled, all received characters (except c5.0) are written to the elasticity buffer, regardless of the state or configuration of any present address match. this allows one or more sources to send data to multiple receivers with the receivers connected in a ring or daisy-chain topology. by prefacing cells containing data with an address field, it is possible to have each receiver only process data specifically directed to it. byte-unpacker the byte-unpacker is used to re-assemble 10-bit characters from a received stream of decoded 8-bit characters. this re- assembly process is designed to allow transmission of the same embedded commands, serial addresses, and start of cell markers that are used with 8-bit data characters. because of the change in time per received encoded character versus delivered 10-bit data character, this unpacking process is only possible with the receive fifo enabled. the byte-unpacker reverses the character segmentation shown in figure 4 . it takes five data characters and combines them into four 10-bit characters. this five-state unpacking pro- cess is re-started by the detection of any special character code in the decoder, including the c5.0 (k28.5) fill character. since usage of the elasticity buffer inserts and deletes c5.0 characters (as necessary) to handle the speed differences be- tween the receive and transmit character clocks, it is not pos- sible to send byte-packed data through the elasticity buffer. to send 10-bit packed data from one source to multiple destina- tions it is necessary to either use a star topology of intercon- nect, or make use of the buffered and reclocked serial input- to-output connections controlled by the routing matrix. parity generation parity generation is enabled only when the receive fifo is bypassed (fifobyp* is low) and the decoder is enabled (encbyp* is low). in this mode odd parity is provided on the rxdata[8] output. this ensures that at least one bit of the data bus is always a logic-1. the generated odd parity is valid for the rxd[7:0], rxsc/d*, and rxrvs signals. receive control state machine the receive control state machine responds to multiple input conditions to control the routing and handling of received char- acters. it controls the staging of characters across various reg- isters and the receive fifo. it also interprets all embedded special character codes, and converts the appropriate ones to specific bit combinations in the receive fifo. it controls the various discard policies and error control within the receiver, and operates in response to: the received character stream the detection and validation of serial addresses the room for additional data in the receive fifo the state of the receiver bist enable (rxbisten*) the state of looptx the state of fifobyp*
cy7c924dx 22 these signals and conditions are used by the receive control state machine to control the receive formatter, write access to the receive fifo, write access to the elasticity buffer, the byte-unpacker, the receive output register, and bist. they determine the content of the characters passed to each of these destinations, the receive control state machine always operates synchro- nous to the recovered character clock (bit-clock/10 or bit- clock/12). when the receive fifo is bypassed, rxclk be- comes an output that changes synchronous to the internal character clock. rxclk operates at the same frequency as the internal character clock. discard policies when the receive fifo is enabled, the receive control state machine has the ability to selectively discard specific charac- ters from the data stream that are determined by the present configuration as being unnecessary. when discarding is en- abled, it reduces the host system overhead necessary to keep the receive fifo from overflowing and losing data. the discard policy is configured as part of the operating mode and is set using the rxmode[1:0] inputs. the four discard policies are listed in table 6 . policy 0 is the simplest and also applies for all conditions where the receive fifo is bypassed. in this mode, every char- acter that is received is placed into the receive fifo (when enabled) or into the receive output register. in discard policy 1, all start of cell, extended command, and serial address commands are processed as they are received. the c5.0 character, which is automatically transmitted when no data is present in the transmit fifo, is treated differently here. in this mode, whenever two or more adjacent c5.0 char- acters are received, all of them are discarded except the last one received before any other character type. this allows these fill characters to be removed from the data stream, but does not change the data flow for protocols (like fibre chan- nel) that use a single c5.0 character as a delimiter. policy 2 is identical to policy 1 except that all c5.0 characters are removed from the data stream. policy 3 is a super-set of policy 2, where the serial address is also discarded. when the fifos are bypassed (fifobyp* low), no charac- ters are actually discarded, but the receiver discard policy can be used to control external filtering of the data. the rxempty* fifo flag is used to indicate if the character on the output bus is valid or not. in discard policy 0, the rxempty* flag is always deasserted to indicate that valid data is always present. in discard policy 1, the rxempty* flag indicates an empty condition for all but the last c5.0 character before any other character is presented. in discard policies 2 or 3, the rxempty* flag indicates an empty condition for all c5.0 characters. when any other character is present, this flag indicates that valid or ? interesting ? data or special characters are present. receive fifo the receive fifo is used to buffer data captured from the selected serial stream for later processing by the host system. this fifo is sized to hold 256, 14-bit characters. when the fifo is enabled, it is written to by the receive control state machine. when data is present in the receive fifo (as indi- cated by the rxfull*, rxhalf*, and rxempty* receive fifo status flags), it can be read from the output register by asserting am* and rxen*. the read port on the receive fifo may be configured for the same two timing models as the transmit interface: utopia and cascade. both are forms of a fifo interface. the utopia timing model has active low rxempty* and rxfull* sta- tus flags, and an active low rxen* enable. when configured for cascade operation, these same signals are all active high. either timing model supports connection to various host bus interfaces, state machines, or external fifos for depth expansion (see figure 5 ). the receive fifo presents full, half-full, and empty fifo status flags. these flags are provided synchronous to rxclk to allow operation with a moore-type external controlling state machine. when configured with the receive fifo enabled, rxclk is an input. when the receive fifo is bypassed (fifobyp* is low), rxclk is an output operating at the re- ceived character rate. receive input register the input register is clocked by the rising edge of rxclk. it samples numerous signals that control the reading of the re- ceive fifo and operation of the receive control state ma- chine. receive output register the receive output register changes in response to the ris- ing edge of rxclk. the receive fifo status flag outputs of this register are placed in a high-z state when the cy7c924dx is not addressed (am* is sampled high). the table 6. receiver discard policies policy # policy description 0 keep all received characters 1 process commands, discard all but the last c5.0 character 2 process commands, discard all c5.0 characters 3 process commands, discard all c5.0 characters, discard serial addresses figure 5. external fifo depth expansion of the cy7c924dx receive data path ef* ren* d rxclk ef* ren* d rclk ff* wen* q wclk rxen rxempty rxdata rxclk rxsc/d* cy7c42x5 fifo cy7c924dx extfifo ? 1 ?
cy7c924dx 23 rxdata bus output drivers are enabled when the device is selected by rxen* being asserted in the rxclk cycle imme- diately following that in which the device was addressed (am* is sampled low), and rxen* being sampled by rxclk. this initiates a receive fifo read cycle. just as with the txdata bus on the transmit input register, the receive outputs are also mapped by the specific decoding, parity, and bus-width selected by the encbyp*, byte8/10* and fifobyp* inputs. these assignments are shown in ta ble 7 . when the decoder and receive fifo are both enabled, the receive control state machine interprets and discards (ex- cept in discard policy 0) received c0.0 and c3.0 command codes as set and clear directives for the rxint output. this allows the rxint output to duplicate the state transitions pre- sented to the txint input at the source end of the link. this rxint output can be used, along with txhalt*, txint, and rxhalf*, to implement a back-pressure mechanism for the receive fifo, or for other time dependent signalling. table 7. receive output bus signal map receive decoder mode [1] decoded 10-bit character stream (8-bit characters) undecoded 10-bit character stream decoded 10-bit byte-packed character stream (10-bit characters) undecoded 12-bit character stream encbyp* high low high low byte8/10* high high low low rxdata bus i/o bit rxsc/d* rxsc/d* rxsc/d* rxdata[0] rxd[0] rxd[0] [5] rxd[0] rxd[0] [5] rxdata[1] rxd[1] rxd[1] rxd[1] rxd[1] rxdata[2] rxd[2] rxd[2] rxd[2] rxd[2] rxdata[3] rxd[3] rxd[3] rxd[3] rxd[3] rxdata[4] rxd[4] rxd[4] rxd[4] rxd[4] rxdata[5] rxd[5] rxd[5] rxd[5] rxd[5] rxdata[6] rxd[6] rxd[6] rxd[6] rxd[6] rxdata[7] rxd[7] rxd[7] rxd[7] rxd[7] rxint/rxop/rxdata[8] (fifobyp*=high) rxint rxd[8] rxd[8] rxd[8] rxint/rxop/rxdata[8] (fifobyp*=low) rxop rxd[8] rxd[8] rxd[8] rxdata[9] (low) rxd[9] rxd[9] rxd[9] rxrvs/rxdata[10] rxrvs rxrvs rxd[10] rxsoc/rxdata[11] rxsoc rxsoc rxd[11] note: 5. first bit shifted in. others follow in numerical order interpreted from an nrz pattern.
cy7c924dx 24 if the receive fifo and decoder are bypassed, all received characters are passed directly to the receive output register. if framing is enabled, and k28.5 characters have been detect- ed meeting the present framing requirements, the output char- acters will appear on proper character boundaries. if framing is disabled (rfen is low) or k28.5 characters have not been detected in the data stream, the received characters may not be output on their proper 10-bit boundaries. in this mode, some form of external framing and decoding/descrambling must be used to recover the original source data. serial address register the receiver is capable of selectively accepting or discarding received data based on an address received in the data stream. the address matching capability allows for the choice of matching of either domains (multicast) or exact addresses (unicast). the 8- or 10-bit serial address register represents a single character address field as shown in figure 6 . the multicast mode is bit-specific and allows allocation of up to 8 or 10 separate domains. in the unicast address mode the match is character specific and identifies up to 256 or 1024 destination addresses. a device can either belong to one or more domains, or it can have a single unique address. when a serial address is received and a match is detected, the address, and all data following that address, is passed to the receive fifo (except in discard policy 3 where the address is discarded). this continues until a serial address is received that does not match the contents of the address register, whereupon writes to the receive fifo are inhibited. the serial address register has a power-up default state where the multicast field set to an all ones condition (ffh or 3ffh). when set to this value the receiver accepts all data, regardless of the of the presence or content of any received serial address. this ? promiscuous ? address can also be forced by the momentary assertion of the reset*[1:0] pair. the serial address register is only used when the receiver is operated with the receive fifo enabled (fifobyp* is high) and in operating modes where the discard policy is not 0 (see ta ble 6 for a list of discard policies). serial address register access the serial address register is accessed through the rxdata bus. both reads and writes to the register require the device to be addressed (am* is low) and for rxrst* to be asserted (low). when accessed for write or read operations, the rxrvs signal is used as a read/write selector, and rxsc/d* is used to select the operating mode (multicast or unicast) of the serial address register. serial address register lsb msb address register content rxdata[0] rxdata[9] or [7] figure 6. serial address register format and access unicast address write unicast address read multicast address write 1 0 1 rxsc/d* multicast address read 0 rxrvs 0 1 0 1 rxrst* 0 0 0 0 rxen* 0 0 0 0
cy7c924dx 25 cy7c924dx dc electrical characteristics over the operating range parameter description test conditions min. max. unit ttl outputs v oht output high voltage i oh = ? 2ma, v dd = min 2.4 v v olt output low voltage i ol = 8 ma, v dd = min 0.4 v i ost output short circuit current v out = 0v [6] ? 30 ? 80 ma i ozl high-z output leakage current ? 20 20 a ttl inputs v iht input high voltage 2.0 v cc v v ilt input low voltage ? 0.5 0.8 v i iht input high current v in = v cc +40 a i ilt input low current v in = 0.0v ? 40 a i ihpd input high current v in = v cc , pins with internal pull-down +300 a i ilpu input low current v in = 0.0v, pins with internal pull-up ? 300 a transmitter pecl-compatible output pins: outa+, outa ? , outb+, outb ? [7] v ohe output high voltage (v dd referenced) load = 50 ? to v cc ? 1.33v r curset = 10k v dd ? 1.03 v dd ? 0.83 v v ole output low voltage (v dd referenced) load = 50 ? to v cc ? 1.33v r curset = 10k v dd ? 2v dd ? 1.62 v v odif output differential voltage |(out+) ? (out ? )| load = 50 ? to v cc ? 1.33v r curset = 10k 600 1100 mv receiver single-ended pecl-compatible input pin: cardet v ihe input high voltage (v dd referenced) v dd ? 1.165 v dd v v ile input low voltage (v dd referenced) 2.5 v dd ? 1.475 v i ihe input high current v in = v ihe (min.) +40 a i ile input low current v in = v ile (max.) ? 40 a differential line receiver input pins: ina+, ina ? , inb+, inb ? v diff input differential voltage |(in+) ? (in ? )| 200 2500 mv v ihh highest input high voltage v dd v v ill lowest input low voltage 2.5 v i ihh input high current v in = v ihh max. 750 a i ill [8] input low current v in = v ill min. ? 200 a miscellaneous typ. max. i dd [9] power supply current freq. = max. 170 250 ma capacitance [10] parameter description test conditions max. unit c inttl ttl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 7 pf c inpecl pecl input capacitance t a = 25 c, f 0 = 1 mhz, v dd = 5.0v 4 pf notes: 6. tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 7. the output current and (resulting voltage swing) is set using a single resistor between cursetx and v ss . this curset resistor value is calculated as r curset = (100 *z o )/v odif , where z o is the differential load between the true and compliment outputs of the differential driver. 8. to guarantee positive currents for all pecl voltages, an external pull-down resistor must be present. 9. maximum i dd is measured with v dd = max, rfen = low, and outputs unloaded. typical i dd is measured with v dd = 5.0v, t a = 25 c, rfen = low, and outputs unloaded. 10. tested initially and after any design or process changes that may affect these parameters, but not 100% tested.
cy7c924dx 26 ac test loads and waveforms 2.0v 0.8v 3.0v 0.0v 2.0v 0.8v 5.0v output (a) ttl ac test load (b) pecl ac test load 1 ns 80% 20% 80% 20% (c) ttl input test waveform (d) pecl input test waveform r1 r2 c l c l r l r1 = 500 ? r2 = 333 ? (includes fixture and probe capacitance) r l = 50 ? c l <5pf (includes fixture and probe capacitance) v ihe 3.0v v dd ? 1.33v v ihe v ile v ile [11] [11] v th =1.5v v th =1.5v 1 ns c l 10 pf note 11 1 ns 1 ns cy7c924dx transmitter ttl switching characteristics, fifo enabled over the operating range parameter description min. max. unit f ts txclk clock cycle frequency with transmit fifo enabled 50 mhz t txclk txclk period 20 ns t txcpwh txclk high time 6.5 ns t txcpwl txclk low time 6.5 ns t txclkr [10] txclk rise time [12] 0.7 5 ns t txclkf [10] txclk fall time [12] 0.7 5 ns t txa flag access time from txclk to output 2 15 ns t txds transmit data set-up time to txclk 4ns t txdh transmit data hold time from txclk 1ns t txens transmit enable set-up time to txclk 4ns t txenh transmit enable hold time from txclk 1ns t txrss transmit fifo reset (txrst*) set-up time to txclk 4ns t txrsh transmit fifo reset (txrst*) hold time from txclk 1ns t txams transmit address match (am*) set-up time to txclk 4ns t txamh transmit address match (am*) hold time from txclk 1ns t txza sample of am* low by txclk , output high-z to active high or low 0 ns t txoe sample of am* low by txclk to output valid 1.5 20 ns t txaz sample of am* high by txclk to output in high-z 1.5 20 ns notes: 11. cypress uses constant current (ate) load configurations and forcing functions. this figure is for reference only. 12. input/output rise and fall time is measured between 0.8v and 2.0v.
cy7c924dx 27 cy7c924dx receiver ttl switching characteristics, fifo enabled over the operating range parameter description min. max. unit f ris rxclk clock cycle frequency with receive fifo enabled 50 mhz t rxclkip rxclk input period 20 ns t rxcpwh rxclk input high time 6.5 ns t rxcpwl rxclk input low time 6.5 ns t rxclkir [10] rxclk input rise time [12] 0.7 5 ns t rxclkif [10] rxclk input fall time [12] 0.7 5 ns t rxens receive enable set-up time to rxclk 4ns t rxenh receive enable hold time from rxclk 1ns t rxrss receive fifo reset (rxrxt*) set-up time to rxclk 4ns t rxrsh receive fifo reset (rxrxt*) hold time from rxclk 1ns t rxams receive address match (am*) set-up time to rxclk 4ns t rxamh receive address match (am*) hold time from rxclk 1ns t rxa [13] flag and data access time from rxclk to output 1.5 15 ns t rxza [13] sample of am* low by rxclk , output high-z to active high or low, or sample of rxen* asserted by rxclk , output high-z to active high or low 0ns t rxoe [13] sample of am* low by rxclk to output valid, [13] or sample of rxen* asserted by rxclk to rxdata outputs valid 1.5 20 ns t rxaz [13] sample of am* high by rxclk to output in high-z, [13] or sample of rxen* deasserted by rxclk to rxdata outputs in high-z 1.5 20 ns cy7c924dx transmitter ttl switching characteristics, fifo bypassed over the operating range parameter description min. max. unit t tra flag access time from refclk to output 2 15 ns t refds write data set-up time to refclk 4 ns t refdh write data hold time from refclk 2 ns t refens transmit enable set-up time to refclk 4 ns t refenh transmit enable hold time from refclk 2 ns t refams transmit address match (am*) set-up time to refclk 4 ns t refamh transmit address match (am*) hold time from refclk 2 ns t refza sample of am* low by refclk , output high-z to active high or low 0 ns t refoe sample of am* low by refclk to flag output valid 1.5 20 ns t refaz sample of am* high by refclk to flag output high-z 1.5 20 ns note: 13. parallel data output specifications are only valid if all outputs are loaded with similar dc and ac loads.
cy7c924dx 28 cy7c924dx receiver ttl switching characteristics, fifo bypassed over the operating range parameter description min. max. unit f ros [14] rxclk clock output frequency ? 100 to 200 mbaud (rangesel is high, encbyp* is high or byte8/10* is high) 10 20 mhz rxclk clock output frequency ? 50 to 100 mbaud (rangesel is low, encbyp* is high or byte8/10* is high) 510mhz rxclk clock output frequency ? 100 to 200 mbaud 12-bit encoder bypass operation (rangesel is high, encbyp* is low and byte8/10* is low) 8.33 16.67 mhz rxclk clock output frequency ? 50 to 100 mbaud 10-bit operation (rangesel is low, encbyp* is low and byte8/10* is low) 4.16 8.33 mhz t rxclkop rxclk output period 25 250 ns t rxclkod rxclk output duty cycle 40 60 % t rxclkor [10] rxclk output rise time [12] 0.25 2 ns t rxclkof [10] rxclk output fall time [12] 0.25 2 ns t rxens receive enable set-up time to rxclk 4ns t rxenh receive enable hold time from rxclk 1ns t rxza [13] sample of am* low by rxclk , outputs high-z to active sample of rxen* asserted by rxclk to rxdata outputs high-z to active 0ns t rxoe [13] sample of am* low by rxclk to flag output valid sample of rxen* asserted by rxclk to rxdata output low-z 1.5 20 ns t rxaz [13] sample of am* high by rxclk to flag output high-z sample of rxen* deasserted by rxclk to rxdata output high-z 1.5 20 ns cy7c924dx receiver switching characteristics over the operating range parameter description min. max. unit t b [17] bit time 5.0 20.0 ns t in_j in peak-to-peak input jitter tolerance [15, 16] 0.5 ui t sa static alignment [10, 18] 600 ps t efw error free window [10, 15, 19] 0.65 ui notes: 14. the period of f ros will match the period of the transmitter pll reference (refclk) when receiving serial data. when data is interrupted, rxclk ma y drift to refclk 2500 ppm. 15. receiver ui (unit interval) is calculated as 1/(f ref * 10) when operated in 8-bit mode if no data is being received, or 1/(f ref *10) of the remote transmitter if data is being received. in an operating link this is equivalent to 10 * t b . when refclk = 1x the character rate. these equations change to 1/(f ref * 12) when operated in 10-bit mode with the encoder bypassed. at alternate multiply ratios (2x or 4x, as selected by spdsel and rangesel), the numerator is multiplied by 2 or 4 respectively. 16. the specification is sum of 25% duty cycle distortion (dcd), 10% data dependant jitter (ddj), 15% random jitter (rj). 17. the pecl switching threshold is the midpoint between the v ohe , and v ole specifications (approximately v dd ? 1.33v). 18. static alignment is a measure of the alignment of the receiver sampling point to the center of a bit. static alignment is me asured by the absolute difference of the left and right edge shifts (|t sh_l - t sh_r |) of one bit until a character error occurs. 19. error free window is a measure of the time window between bit centers where a transition may occur without causing a bit sam pling error. efw is measured over the operating range, input jitter < 50% dj.
cy7c924dx 29 cy7c924dx transmitter switching characteristics over the operating range parameter description min. max. unit t b [17] bit time 5.0 20.0 ns t rise pecl output rise time 20 ? 80% (pecl test load) [10] 200 1700 ps t fa ll pecl output fall time 80 ? 20% (pecl test load) [10] 200 1700 ps t dj deterministic jitter (peak-peak) [10, 20] 0.02 ui t rj random jitter ( ) [10, 21] 0.008 ui t jt transmitter total output jitter (pk-pk) [10] 0.08 ui cy7c924dx refclk input switching characteristics over the operating range parameter description conditions min. max unit spdsel rangesel byte8/10* f ref refclk clock frequency ? 50 to 100 mbaud, 10-bit mode, encoder bypass, refclk = 2x character rate 0 0 0 8.33 16.67 mhz refclk clock frequency ? 50 to 100 mbaud, 8-bit mode, refclk = 2x character rate 00 11020mhz refclk clock frequency ? 50 to 100 mbaud, 10-bit mode, encoder bypass, refclk = 4x character rate 01 [22] 0 16.67 33.33 mhz refclk clock frequency ? 50 to 100 mbaud, 8-bit mode, refclk = 4x character rate 01 [22] 12040mhz refclk clock frequency ? 100 to 200 mbaud, 10-bit mode, encoder bypass, refclk = character rate 1 0 0 8.33 16.67 mhz refclk clock frequency ? 100 to 200 mbaud, 8-bit mode, refclk = character rate 10 11020mhz refclk clock frequency ? 100 to 200 mbaud, 10-bit mode, encoder bypass, refclk = 2x character rate 1 1 0 16.67 33.3 mhz refclk clock frequency ? 100 to 200 mbaud, 8-bit mode, refclk = 2x character rate 11 12040mhz t refclk refclk period 25 120 ns t refh refclk high time 6.5 ns t refl refclk low time 6.5 ns t refrx refclk frequency referenced to received clock period [23] ? 0.04 +0.04 % notes: 20. while sending continuous k28.5s, outputs loaded to 50 ? to v dd ? 1.33v, over the operating range. 21. while sending continuous k28.7s, after 100,000 samples measured at the cross point of differential outputs, time referenced to refclk input, over the operating range. 22. when configured for synchronous operation with the fifos bypassed (fifobyp* is low), if rangesel is high the spdsel input is ignored and operation is forced to the 100 ? 200 mbaud range. 23. refclk has no phase or frequency relationship with rxclk and only acts as a centering reference to reduce clock synchronizat ion time. refclk must be within 0.04% of the transmitter pll reference (refclk) frequency, necessitating a 200-ppm crystal.
cy7c924dx 30 cy7c924dx hotlink transmitter switching waveforms notes: 24. when transferring data to the transmit fifo from a depth expanded external fifo, the data is captured from the external fifo one clock cycle following the actual enable. 25. when writing data from a utopia compliant interface, the write data is captured on the same clock cycle as the data. no operation t txa t txa txclk asynchronous (fifo) interface t txclk t txclkh t txclkl txdata[11:0] , txsc/d* txen txfull txhalf* txempty t txds t txdh t txens t txenh note 24 txperr cascade timing write cycle no operation t txa txclk txdata[11:0], txsc/d* txen* txfull* txhalf* txempty* t txdh t txds t txclk t txclkh t txclkl t txens t txenh note 25 txperr t txa asynchronous (fifo) interface utopia timing write cycle
cy7c924dx 31 note: 26. transmit fifo writes are permitted while the status flag outputs are high-z, however operation in this mode is not encourage d since this may mask a fifo full condition, causing data to be lost. cy7c924dx hotlink transmitter switching waveforms (continued) no operation txclk txdata[11:0], txsc/d* txen* txfull* txhalf* txempty* t txdh t txds t txclk t txclkh t txclkl t txens t txenh am* note 26 t txoza t txoe t txoaz txperr t txams t txrss txrst* t txamh, t txrsh, asynchronous (fifo) interface output enable timing no operation t tra t tra refclk synchronous interface t refclk t refh t refl txdata[11:0] , txsc/d* txen txfull txhalf* txempty t refds t refdh t refens t refenh note 24 txperr cascade timing write cycle
cy7c924dx 32 cy7c924dx hotlink transmitter switching waveforms (continued) no operation t tra refclk txdata[11:0], txsc/d* txen* txfull* txhalf* txempty* t refdh t refds t refclk t refh t refl t refens t refenh note 25 txperr t tra synchronous interface utopia timing write cycle no operation refclk txdata[11:0], txsc/d* txen* txfull* txhalf* txempty* t refdh t refds t refclk t refh t refl t refens t refenh am* note 26 t refoza t refoe t refoaz txperr t refams t refamh synchronous interface output enable timing
cy7c924dx 33 cy7c924dx hotlink receiver switching waveforms notes: 27. when transferring data from the receive fifo to a depth expanded external fifo, the data is sent to the external fifo on the same clock cycle an rxempty indicates the data is available. 28. on inhibited reads, or if the receive fifo goes empty, the data outputs do not change. 29. when reading data from a utopia compliant interface, the data is captured on the same clock cycle as the fifo flag indicates data available, and not when the fifo indicates empty. cascade timing read cycle no operation rxclk rxempty rxen valid data t rxclkip t rxclkih t rxclkil t rxens t rxenh am* rxdata[11:0] rxsc/d* rxint, lfi* rxfull rxhalf* t ra read read t ra note 27 note 28 fifo empty t rxclkop t rxclkoh t rxclkol utopia timing read cycle rxclk rxempty* rxen* valid data t rxclkip t rxclkih t rxclkil t rxiens t rxienh, t rxoenh am* rxdata[11:0] rxsc/d* rxint, lfi* rxfull* rxhalf* t ra read t ra note 29 fifo empty t rxclkop t rxclkoh t rxclkol t rxoens
cy7c924dx 34 note: 30. receive fifo reads are inhibited while the outputs are high-z or rxbisten* is active. cy7c924dx hotlink receiver switching waveforms (continued) output enable timing no operation rxclk rxen* rxfull* rxhalf* rxempty* t rxclk t rxclkh t rxclkl t rxiens t rxienh, t rxoenh am* t rxooza t rxoe t rxaz rxdata[11:0] rxint rxsc/d* old data note 30 t rxioza t rxiams t rxiamh, t rxoamh t rxoams t rxoens refclk t refl t refh t refclk ina inb t b /2 ? t sa t b /2 ? t sa static alignment sample window ina inb t b t efw bit center bit center error-free window
cy7c924dx 35 cy7c924dx hotlink transceiver operation the interconnection of two or more cy7c924dx transceivers form a general-purpose communications subsystem capable of transporting user data at up to 20 mbytes per second over several types of serial interface media. the cy7c924dx is highly configurable with multiple modes of operation. in the transmit section of the cy7c924dx, data moves from the input register, through the transmit fifo, to the 8b/10b encoder. the encoded data is then shifted serially out the outx differential pecl compatible drivers. the bit-rate clock is generated internally from a 2.5x, 5x, or 10x pll clock mul- tiplier. a more complete description is found in the section cy7c924dx hotlink transmit-path operating mode de- scription . in the receive section of the cy7c924dx, serial data is sam- pled by the receiver on one of the inx differential line receiver inputs. the receiver clock and data recovery pll locks onto the selected serial bit stream and generates an internal bit-rate sample clock. the bit stream is deserialized, decoded, and presented to the receive fifo, along with a character clock. the data in the fifo can then be read either slower or faster than the incoming character rate. a more complete description is found in the section cy7c924dx hotlink receive-path operating mode description . the transmitter and receiver parallel interface timing and functionality can be configured to cascade directly to external fifos for depth expansion, to emulate a utopia interface, couple directly to registers, or couple directly to state ma- chines. these interfaces can accept or output either: 8-bit characters 10-bit characters (for byte-packed encoded transport) 10-bit pre-encoded characters (pre-scrambled or pre-encoded) 12-bit pre-encoded characters (pre-scrambled or pre-encoded) the bit numbering and content of the parallel transmit interface is shown in ta ble 1 . when operated with the 8b/10b encoder bypassed, the txsc/d* and rxsc/d* bits are ignored. the hotlink transceiver serial interface provides a seamless interface to various types of media. a minimal number of ex- ternal passive components are required to properly terminate transmission lines and provide lvpecl loads. for power sup- ply decoupling, a single capacitor (in the range of 0.02 f to 0.1 f) is required per power/ground pair. additional informa- tion on interfacing these components to various media can be found in the hotlink design considerations application note. cy7c924dx hotlink transmit-path operating mode descriptions the hotlink transmitter can be configured into several oper- ating modes, each providing different capabilities and fitting different transmission needs. these modes are selected using the fifobyp*, encbyp* and byte8/10* inputs on the cy7c924dx transceiver. these modes can be reduced to five primary classes: synchronous encoded synchronous pre-encoded asynchronous encoded asynchronous byte-packed asynchronous pre-encoded synchronous encoded in this mode, the transmit fifo is bypassed, while the 8b/10b encoder is enabled. one character is accepted at the transmit input register at the rising edge of refclk, and passed to the encoder where it is encoded for serial transmission. the serializer operates synchronous to refclk, which is multi- plied by 10 or 5 to generate the serial data bit-clock. in this mode the txsoc, txrst*, txint, txhalt*, and txstop* inputs (when they are not used for data bits) are not interpreted and may be tied either high or low. to place the cy7c924dx into synchronous modes, fifobyp* must be low. this mode is usually used for products that must meet specific predefined protocol requirements, and cannot tolerate the un- controlled insertion of c5.0 fill characters. the host system is required to provide new data at every rising edge of refclk (along with txen*) to maintain the data stream. if txen* is not asserted, the encoder is loaded with c5.0 (k28.5) sync characters. because the encoder is enabled, the transmitted c5.0 characters follow all 8b/10b encoding rules. input register mapping in encoded modes, the bits of the txdata input bus are mapped into characters (as shown in table 1 ), including a txsvs bit, eight bits of data, and a txsc/d* bit to select either special character codes or data characters. when the inter- nal fifo is enabled, txint and txsoc bits are associated with the txdata bus. when the internal fifo is disabled txparen and txopin are associated with the txdata bus. when parity generation is enabled (txparen is high) the txopin bit is interpreted as the odd parity for the remaining bits of the character. when parity generation is disabled (txparen is low) the txopin bit is ignored if the txsvs bit is high, an svs (c0.7) character is passed to the encoder, regardless of the contents of the other txdata inputs. if the txsvs bit is low, the associated txdata char- acter is encoded per the remaining bits in that character. the txsc/d* bit controls the encoding of the txdata[7:0] or txdata[9:0] bits of each character. it is used to identify if the input character represents a data character or a special character code. if txsc/d* is low, the character is encoded using the data character codes listed in table 10 . if txsc/d* is high, the character is encoded using the special character codes listed in table 11 . parity synchronous encoded operation allows parity checking of all characters written to the transmit input register. if a parity error is detected the txperr output goes high for one refclk period. the specific character or characters having parity errors are replaced at the encoder with the svs (c0.7) character, which may then be detected at the remote receiver. synchronous pre-encoded in synchronous pre-encoded mode, both the transmit fifo and the 8b/10b encoder are bypassed, and data passes di- rectly from the transmit input register to the serializer. the serializer operates synchronous to refclk, which is multi-
cy7c924dx 36 plied by 10 or 5 when byte8/10* is high (as selected by the spdsel and rangesel inputs) to generate the serial data bit-clock. in this mode the txint, txhalt*, txsvs and txsoc inputs are used as part of the data input bus. to place the cy7c924dx into synchronous modes, fifobyp* must be low. this mode is usually used for products containing external en- coders or scramblers, that must meet specific protocol require- ments. the host system is required to provide new data at every rising edge of the refclk (along with txen*) to main- tain the data stream. if txen* is not asserted, the serializer is loaded with c5.0 (k28.5) sync characters. however, because the bypassed encoder is not able to track the running disparity of the previously transmitted character, the transmitted c5.0 characters may be received with a running disparity code-rule violation. in this mode the lsb of each input character (txdata[0]) is shifted out first, followed sequentially by txdata[1] through txdata[9]. asynchronous encoded asynchronous encoded mode is the most powerful operating mode of the cy7c924dx. both the transmit fifo and the encoder are enabled. this allows transmission of normal data streams, while offering the added benefits of embedded cell or packet markers, an expanded command set, serial address- ing, and in-band bypass-signaling (for flow control or other pur- poses). the serializer operates synchronous to refclk, which is multiplied by 2.5, 5, or 10 to generate the serial data bit-clock (as selected by spdsel and rangesel). in this mode the txsoc, txrst*, txint, txhalt*, and txstop* inputs are interpreted. this mode supports the same input register mapping as syn- chronous encoded mode, with the addition of the txsoc bit. because both the transmit fifo and encoder are enabled, the input fifo may be loaded at any rate supported by the fifo (up to 50 mhz), without generating any decoder errors at the receive end of the link. all characters added to the data stream to support these additional capabilities may be automatically extracted by the receive control state machine in the cy7c924dx receiver. embedded cell marker an embedded cell marker is used to mark the start of cells or frames of information passed from one end of the link to the other. this marker is set by asserting txsoc high, with txsc/d* and txsvs both low, along with the remaining data on the txdata bus. when the character (or characters) accompanying this marker is read from the output end of the transmit fifo, a c8.0 (k23.7) character is inserted into the data stream prior to the following data characters being read from the transmit fifo. expanded commands the standard 8b/10b character set contains all 256 possible data characters, but only twelve special or command charac- ters. to allow use of a larger selection of command codes, a special character code was selected to expand the command set. an expanded command marker is used to mark the associated data as any one of 256 (2 8 ) possible commands codes. this marker is generated by asserting both txsoc and txsc/d* high, with txsvs being low, along with the associated data on the txdata bus. when the character accompanying this marker is read from the output end of the transmit fifo, a c9.0 (k27.7) character is inserted into the data stream prior to the data characters read from the transmit fifo. serial addressing the cy7c924dx receiver has the ability to accept or reject data based on an internal address-controlled switch. this switch is turned on when a serial address (matching the re- ceiver address settings) is received. a serial address is transmitted by asserting txsoc, txsc/d*, and txsvs all high. when the character accompanying this marker is read from the output end of the transmit fifo, a c10.0 (k29.7) character is inserted into the data stream prior to the data characters read from the transmit fifo. the serial address is either 8 or 10.bits depending on the level on byte8/10*. in-band bypass-signaling in-band bypass-signaling allows a signal to be sent to the re- mote receiver without that signal having to pass through the transmit (or receive) fifo. when txint transitions from 0 1, a c0.0 (k28.0) special character is sent. when txint transitions from 1 0, a c3.0 (k28.3) special code is sent. these special codes may be used to force a similar signal transition on the rxint output of an attached cy7c924dx hotlink receiver. this input may be used to transport a low data rate signal (like a serial rs-232/uart signal) across the interface, without any significant impact on the actual data being transported across the link. it may also be used to transparently propagate fifo flow control information across the link by directly connecting the rxhalf* flag of the local receiver to the txint of the local transmitter. the rxint at the remote end of the link can then be connected to the txhalt* input to halt data transfers at the remote end of the link until the local receive fifo has suffi- cient room to continue. asynchronous byte-packed asynchronous byte-packed mode contains the same features as asynchronous encoded, but with support for 10-bit source data. this data is byte-packed through the 8b/10b encoder to deliver the data across the interface. when sending extended commands, the larger 10-bit charac- ter size enlarges the extended command space to 1024 (2 10 ) possible commands codes. asynchronous pre-encoded in asynchronous pre-encoded modes, the transmit fifo is enabled. this means that all words clocked into the input reg- ister are written to the transmit fifo before being sent to the serializer. the serializer operates synchronous to refclk, which is multiplied by 10 or 5 (or 6 or 12 when byte8/10* is low) to generate the serial data bit-clock. in this mode the txint and txhalt* inputs are used as part of the 10-bit input character. txsvs, txsoc and txstop* are still available to stop reading of data from the transmit fifo. these modes are usually used for products containing exter- nal encoders or scramblers, that must meet specific protocol requirements. the host system must provide new data at ev- ery rising edge of txclk (along with txen*) to maintain the
cy7c924dx 37 data stream (without overfilling the transmit fifo). if the transmit fifo ever goes empty, the serializer is loaded with an alternating disparity string of c5.0 (k28.5) sync characters (when byte8/10* is high) or the bit pattern 0110000100011 (when byte8/10* is low). depending on the system implementation this can be a signif- icant issue. if the remote receiver is configured to decode 8b/10b coded characters, it will probably detect running dis- parity errors because the bypassed encoder is not able to track the running disparity of the previously transmitted char- acter. however, since these pre-encoded modes are generally used with alternate forms of scrambling or encoding, this is not generally an issue. to maintain a data stream without adding these c5.0 sync codes, it is necessary that the transmit fifo be loaded at or faster than the rate that data is read from that fifo. cy7c924dx hotlink receive-path operating mode descriptions the hotlink receiver can be configured into several operat- ing modes, each providing different capabilities and fitting dif- ferent reception needs. these modes are selected using the fifobyp*, enbyp*, byte8/10* inputs on the cy7c924dx transceiver. these modes can be reduced to five primary classes: synchronous decoded synchronous undecoded asynchronous decoded asynchronous byte-packed asynchronous undecoded in all these modes, serial data is received at one of the differ- ential line receiver inputs and routed to the deserializer and framer. the pll in the clock and data recovery block is used to extract a bit-rate clock from the transitions in the data stream, and uses that clock to capture bits from the serial stream. these bits are passed to the deserializer where they are formed into 10- or 12-bit characters. to align the incoming bit stream to the proper character bound- aries, the framer must be enabled by asserting rfen high. the framer logic-block checks the incoming bit stream for the unique pattern that defines the character boundaries. this log- ic filter looks for the ansi x3.230 symbol defined as a ? special character comma ? (k28.5 or c5.0). once a k28.5 is found, the framer captures the offset of the data stream from the present character boundaries, and resets the boundary to re- flect this new offset, thus framing the data to the correct char- acter boundaries. since noise induced errors can cause the incoming data to be corrupted, and since many combinations of corrupt and legal data can create an aliased k28.5, the framer may also be dis- abled by deasserting rfen low. an option exists in the framer to require multiple k28.5 char- acters, meeting specific criteria, before the character bound- aries are reset. this multi-byte mode of the framer is enabled by keeping rfen asserted high for greater than approxi- mately 2000 character clock cycles. for multi-byte framing, the receiver must find a pair of k28.5 characters, both on identical 10-bit boundaries, within a 5-character span (50 bits). synchronous decoded in these modes, the receive fifo is bypassed, while the 10b/8b decoder is enabled. framed characters output from the deserializer are decoded, and passed direct to the re- ceive output register. the deserializer operates synchronous to the recovered bit-clock, which is divided by 10 generate the output rxclk clock. in this mode the rxrst* input is not interpreted and may be biased either high or low. these modes are usually used for products that must meet specific protocol requirements. new decoded characters are provided at the rxdata outputs once every rising edge of rxclk. if rxempty is asserted high along with the data, the characters in the output register is a c5.0 (k28.5) sync character, and the discard policy is set to non-0. because the decoder is now enabled, all received characters are checked for compliance to the 8b/10b decoding rules. output register mapping the rxdata[11:0] output bus is mapped into a character con- sisting of eight bits of data, and two bits that carry violation and parity information. an accompanying rxsc/d* bit identifies the character as either control or data. the bits accompanying each character are interpreted differ- ently depending on the configuration selected. when parity generation is enabled, the parity bit contains the odd parity of the rxdata bus. when parity generation is disabled, these bits have combina- tions that identify the meaning of the remaining bits of the char- acter. if rxrvs is high and rxsc/d* is low, the decoder outputs a c0.7, c1.7, c2.7 or c4.7 in response to reception of either an svs (c0.7) character or other invalid character. parity synchronous decoded modes allows odd parity generation on all decoded characters. if characters are detected with par- ity errors in the transmitter, they will have been replaced with the svs (c0.7) character. if a c0.7 character is received it may be an indication of a parity error at the transmitter. synchronous undecoded in this mode, both the receive fifo and the 10b/8b decoder are bypassed, and data passes directly from the deserializer to the output register. the deserializer operates synchronous to the recovered bit-clock, which is divided by 10 to generate the output rxclk clock. in this mode the rxrst* input is not interpreted and may be biased either high or low. this mode is usually used for products containing external de- coders or descramblers that must meet specific protocol re- quirements. new data is provided at the rxdata outputs once every rising edge of rxclk. received characters are not checked for any specific coding requirements and no decoding errors are reported. asynchronous decoded asynchronous decoded modes are the most powerful operat- ing modes of the cy7c924dx hotlink receiver. both the receive fifo and the decoder are enabled. this allows re- ception of normal data streams, while offering the added ben- efits of embedded cell markers, an expanded command set, serial address support, and in-band bypass-signaling (for flow control or other purposes). all characters added to the data stream to support these additional capabilities may be auto-
cy7c924dx 38 matically extracted by the receive control state machine in the cy7c924dx transceiver. the deserializer operates synchronous to the recovered bit- clock, which is divided by 10 to generate the receive fifo write clock. characters are read from the receive fifo, using the external rxclk input, when addressed by am* and se- lected by rxen*. in this mode the rxrst* input is inter- preted. asynchronous decoded modes support the same output register mapping and parity generation capab ilities as the synchronous decoded modes. because both the receive fifo and decoder are enabled, the output fifo may be read at any rate supported by the fifo, however, if the receive fifo ever indicates a full condition (rxfull* is asserted), data may be lost. embedded cell marker an embedded cell marker is used to mark the start of cells or frames of information passed from one end of the link to the other. when a c8.0 (k23.7) character is detected in the data stream, the following character is written to the receive fifo along with rxsoc set high, and rxsc/d* and rxrvs set low. when the character accompanying this marker is read from the receive fifo with these same bits set, it indicates the start of a cell or frame. expanded command the standard 8b/10b character set contains all 256 possible data characters, but only twelve special character codes. to allow use of a larger selection of command codes, one special character code was selected to expand the command set. an expanded command marker is used to mark the associat- ed data as any one of 256 (2 8 ) possible commands codes. when a c9.0 (k27.7) character is detected in the data stream, the following character is written to the receive fifo along with both rxsoc and rxsc/d* set high, and rxrvs set low. when the character accompanying this marker is read from the receive fifo with these same bits set, it may be used to indicate that the data on the rxdata bus is an expanded command. serial addressing the cy7c924dx receive path can be directed to accept all characters, or to only accept that data specifically addressed to it. this address control is managed through an embedded address compare register in the receiver logic. this register supports either domain (multicast) or exact-match (unicast) based compares on an address field received across the serial link. when a c10.0 (k29.7) special code is received, the im- mediately following data character contains the address field that is compared with the receiver serial address register contents. when the cy7c924dx is configured for multicast address matching, the received address field is compared as an or of a bit-wise and with the serial address register. a valid match between any of the bits sets the switch to allow the following data to be written into the receive fifo. when the cy7c924dx is configured for unicast address matching, the received address field is compared for an exact match with the serial address register. if an exact match is found, a switch is set in the receiver to accept all following data until the next serial address marker is found. in-band bypass-signaling in-band bypass-signaling allows a signal to be received at the local receiver without that signal having to pass through the receive (or transmit) fifo. when a c0.0 (k28.0) character is received, the rxint output is set high. when a c3.0 (k28.3) character is received, the rxint output is set low. these special codes are generated by forcing similar transitions into the txint input of the cy7c924dx hotlink transmitter sourcing the data stream. this output may be used to transport a low data-rate signal (like a serial rs-232/uart signal) across the interface, with- out any significant impact on the actual data being transported across the link. it may also be used to transparently propagate fifo flow-control information across the link by directly con- necting the rxhalf* flag of the local receiver to the txint of the local transmitter. the rxint at the remote end of the link can then be connected to the txhalt* input to halt data trans- fers at the remote end of the link until the local receive fifo has sufficient room to continue. asynchronous byte-packed asynchronous byte-packed mode contains the same features as asynchronous decoded, but with support for 10-bit source data. the received characters are decoded first back into 8-bit data characters, which are then re-assembled into 10-bit source data. because of the time difference involved with the packing and unpacking operations, this mode can only be used with the internal fifos enabled. when receiving extended commands, the larger 10-bit char- acter size enlarges the extended command space to 1024 (2 10 ) possible commands codes. when receiving a serial address, the larger 10-bit character size also increases the serial address register to 10 bits. this allows up to 10 separate domains for multicast addressing or 1024 unique addresses for unicast addressing. asynchronous undecoded in asynchronous undecoded modes, the receive fifo is en- abled. this means that all characters received from the serial interface are written to the receive fifo before being passed to the output register. the deserializer operates synchronous to the recovered bit-clock, which is divided by 10 (or 12) to generate the receive fifo write clock. data is read from the receive fifo, using the rxclk input clock, when addressed by am* and selected by rxen*. these modes are usually used for products containing exter- nal decoders or descramblers, that must meet specific proto- col requirements. new data may be read from the receive fifo any time that the fifo status flags indicate a non-empty condition (rxempty* is deasserted). to ensure that data is not lost, the receive fifo must be read faster than data is loaded into the receive fifo. if the receiver is to provide framed characters, it is necessary for the transmit end to include c5.0 (k28.5) characters in the data stream. this can be done by: operating the transmitter in encoded mode and writing c5.0 characters into the data stream, operating the transmitter in pre-encoded mode and writing the 10-bit value for an encoded c5.0 character to the data stream ( 1100000101 or 0011111010 )
cy7c924dx 39 not enabling the transmitter when it is operated in synchro- nous mode, or by allowing the transit fifo to go empty when it is operated in asynchronous mode. bist operation and reporting the cy7c924dx hotlink transceiver incorporates the same built-in self-test (bist) capability used with the cy7b923/ cy7b933 and cy7c929 hotlink components. this link diag- nostic uses a linear feedback shift register (lfsr) to gen- erate a 511-character repeating sequence that is compared, character-for-character, at the receiver. bist mode is intended to check the entire high-speed serial link at full link-speed, without the use of specialized and expen- sive test equipment. the complete sequence of characters used in bist are documented in the ? hotlink built-in self- te s t ? application note. bist enable inputs there are separate bist enable inputs for the transmit and receive paths of the cy7c924dx. these inputs are both active low; i.e., bist is enabled in its respective section of the de- vice when the bist enable input is determined to be at a logic- 0 level. both bist enable inputs are asynchronous; i.e., they are synchronized inside the cy7c924dx to the internal state machines. bist transmit path the transmit path operation with bist is controlled by the txbisten* input and overrides most other inputs (see figure 7 ). when the transmit fifo is enabled (not bypassed) and txbisten* is recognized internally, all reads from the trans- mit fifo are suspended and the bist generator is enabled to sequence out the 511 character repeating bist sequence. if the transmit control state machine was in the middle of an atomic operation (e.g., sending an extended command) the data character associated with the special character code is transmitted prior to recognition of the txbisten* signal and suspension of fifo data processing. if the recognition occurs in the middle of a data field, the following data is not transmit- ted at that time, but remains in the transmit fifo. once the txbisten* signal is removed, the data in the transmit fifo is again available for transmission. to ensure proper data han- dling at the destination, the transmit host controller should ei- ther use txhalt* or txstop* to prevent transmission of data at specific boundaries, or allow the transmit fifo to complete- ly empty before enabling bist. with transmit bist enabled, the transmit fifo remains avail- able for loading of data. it may be written up to its normal max- imum limit while the bist operation takes place. to allow re- moval of stale data from the transmit fifo, it may also be reset during a bist operation. the reset operation proceeds as doc- umented, with the exception of the information presented on the txempty* fifo status flag. since this flag is used to present bist loop status, it continues to reflect the state of the rxbisten* txbisten* txclk txfull* refclk txen* rxclk rxempty* rxen* am* txdata[9:0] txsc/d* txsoc txsvs txhalf* txempty* rxhalf* rxfull* rxdata[9:0] rxsc/d* rxsoc rxrvs enable tx bist start of tx bist bist loop don ? t care low to enable fifo flags ignore these outputs low to enable rxrvs reads forced to indicate empty by bist enable rx bist start of rx bist wait start of rx bist match bist loop outa outb ina inb a/b* high to select a cy7c924dx error figure 7. built-in self-test illustration
cy7c924dx 40 transmit bist loop status until txbisten* is no longer recog- nized internally. the completion of the reset operation may still be monitored through the txfull* fifo status flag. the txempty* flag, when used for transmit bist progress indication, continues to reflect the active high or active low settings determined by the utopia or cascade timing model selected by extfifo; i.e., when configured for the cascade timing model, the txempty* and txfull* fifo flags are active high, when configured for the utopia timing model the txempty* and txfull* fifo flags are active low. the illustration in figure 7 uses the utopia conventions. when txbisten* is first recognized, the txempty* flag is clocked to a reset state, regardless of the addressed state of the transmit fifo (if am* is low or not), but is not driven out of the part unless am* has been sampled asserted (low). following this, on each completed pass through the bist loop, the txempty* flag is set for one interface clock period (txclk or refclk). the txempty* flag remains set until the interface is ad- dressed and the state of txempty* has been observed. if the device is not addressed (am* is not sampled low), the flag remains set internally regardless of the number of txclk clock cycles that are processed. if the device status is not polled on a sufficiently regular basis, it is possible for the host system to miss one or more of these bist loop indications. a pass through the loop is defined as that condition where the encoder generates the d0.0 state. depending on the initial state of the bist lfsr, the first pass through the loop may occur at substantially less than 511 character periods. follow- ing the first pass, as long as txbisten* remains low, all remaining passes are exactly 511 characters in length. when the transmit fifo is bypassed, the interface is clocked by the refclk signal instead of txclk. while the active or asserted state of the txempty* signal is still controlled by the extfifo, the state of any completed bist loops is no longer preserved. instead, the txempty* flag reflects the dynamic state of the bist loop progress, and is asserted only once every 511 character periods. if the interface is not addressed at the time that this occurs, then the fifo status flags remain in a high-z state and the loop event is lost. bist receive path the receive path operation in bist is similar to that of the transmit path. while the receive fifo is enabled (not by- passed) and rxbisten* is recognized internally, all writes to the receive fifo are suspended. if the receiver had a previ- ous serial address match and was accepting data, no addition- al characters are written to the receive fifo. if the receive data state machine was in the middle of processing a multi- character sequence or other atomic operation (e.g., a start of cell marker and its associated data), the characters associated with the atomic operation are discarded and not written to the receive fifo. upon internal recognition of rxbisten*, the serial address match flag is cleared such that once bist has been disabled and data is again being received, all received data is rejected until a new serial address is again received that matches the address match criteria. note: if the cy7c924dx is set to match all data (all 1s in the multicast match field), then it is not necessary to get an address match before receiving data following the termina- tion of bist. when reset or programmed to this state, the device ignores all serial address commands and matches all data. any data present in the receive fifo when rxbisten* is recognized remains in the fifo and cannot be read until the bist operation is complete. the data in the receive fifo re- mains valid, but is not available for reading through the host parallel interface. this is because the error output indicator for receive bist operations is the rxrvs signal, which is normal- ly part of the rxdata bus. to prevent read operations while bist is in operation, the rxempty* and rxhalf* flags are forced to indicate an empty condition. once rxbisten* has been removed and recognized internally, the receive fifo status flags are updated to reflect the current content status of the receive fifo. to allow removal of stale data from the receive fifo, it may be reset during a bist operation. the reset operation pro- ceeds as documented, with the exception that the rxempty* and rxhalf* status flags already indicate an empty condi- tion. the rxfull* flag is used to present bist progress. the active (asserted) state on rxfull* (and rxempty*) remain controlled by the present operating mode and interface timing model (utopia or cascade). when rxbisten* has been recognized, rxfull* becomes the receive bist loop indicator (regardless of the logic state of fifobyp*). when rxbisten* is first recognized, the rxfull* flag is clocked to a set state, regardless of the ad- dressed state of the receive fifo (if am* is sampled low or not). following this, rxfull* remains set until the receiver detects the start of the bist pattern. then rxfull* is deas- serted for the duration of the bist pattern, pulsing asserted for one rxclk period on the last symbol of each bist loop. if 14 of 28 consecutive characters are received in error, rxfull* returns to the set state until the start of a bist se- quence is again detected. just like the bist status flag on the transmit data path, the rxfull* flag captures the asserted states, and keeps them until they are read. this means that if the status flag is not read on a regular basis, events may be lost. the detection of errors is presented on the rxrvs output. unlike the rxfull* fifo status flag, the active state of this output is not controlled by the extfifo input. with the re- ceive fifo enabled, these outputs should operate the same as the rxfull* flag, with respect to preserving the detection state of an error until it is read. unlike the rxfull* flag, which only needs the cy7c924dx to be addressed (am* sampled low by rxclk) to enable the rxfull* three-state driver, and an rxclk to ? read ? the flag, the rxrvs output requires a selection (assertion of rxen* while addressed) to enable the rxdata bus three-state driv- ers. the selection process is necessary to ensure that a multi- phy implementation does not enable multiple rxrvs drivers at the same time. when the receive fifo is bypassed, the interface is clocked by the rxclk output signal. while the active or asserted state of the rxfull* signal is still controlled by the extfifo input, the state of any completed bist loops or detected errors are no longer preserved. instead, the rxfull* flag reflects the dynamic state of the bist loop progress, and is asserted only once every 511 character periods. if the interface is not ad- dressed at the time that this occurs, then the fifo status flags remain in a high-z state and the loop event is lost. this is also
cy7c924dx 41 true of the rxrvs output, such that if the cy7c924dx receive path is not selected to enable the rxdata bus three-state drivers, the detection of a bist miscompare is lost. bist three-state control when bist is enabled on either the transmitter or the receiver, the three-state enable signals for the bist status flags and error indicators work the same as for normal data processing. the output drivers for the bist status that is presented on fifo status flags are only enabled when am* has been sam- pled asserted (low) by the respective clock (txclk, rxclk, or refclk). to access the bist error information, it is necessary to per- form a read cycle of the addressed receiver. this means that am* must be low to allow a receiver address match (rx_match) to exist, and rxen* must be asserted to select the device. because the part is in bist, no data is read from the fifo, but the data bus is driven. this allows the rxrvs indicator to be driven onto the rxdata bus. so long as rxen* remains asserted, the receiver stays selected, the data bus remains driven, and rxrvs has meaning. bus interfacing the parallel transmit and receive host interfaces to the cy7c924dx are configurable for either synchronous or asyn- chronous operation. each of these configurations supports two selectable timing and control models of utopia or cas- cade. all asynchronous bus configurations have the internal trans- mit and receive fifos enabled. this allows data to be written or read from these fifos at any rate up to the maximum 50-mhz clock rate of the fifos. all internal operations of the cy7c924dx do not use the external txclk or rxclk, but instead make use of synthesized derivatives of refclk for transmit path operations and a recovered character clock for receive path operations. all synchronous bus configurations require the bus interface operations to be synchronous to refclk on the transmit path and the recovered clock (output as rxclk) on the receive path. the internal fifos are bypassed in all synchronous modes. the two supported timing and control models are utopia and cascade. these timing models take their name from their de- fault configuration. the utopia timing model is based on the atm forum utopia interface standards. this timing model is that of a fifo with active low fifo status flags and read/write enables. the cascade timing model is a modification of the utopia configuration that changes the flags and fifo read/write en- ables to active high. this model is present primarily to allow depth expansion of the internal fifo by direct coupling to ex- ternal cy7c42x5 synchronous fifos. to allow this direct cou- pling, the cycle-to-cycle timing between the transmit and re- ceive enables (txen* and rxen*) are also modified to ensure correct data transfer. these four configurations of bus operation and timing/control can all be used with or without external fifos. depending on the specific mode selected, the amount of external hardware necessary to properly couple the cy7c924dx to state ma- chines or external fifos is minimal in all cases, and may be zero if the proper configuration is selected. with only minor exceptions, all configurations rely on the com- mon utopia concepts of addressing and selection to control the enabled/disabled state of the output drivers, and when data can be written to or read from the part. utopia interface background the utopia interface is defined by the atm forum as the bus interface between the atm and phy layer devices of an atm system. this interface is defined as 8 or 16 bits wide, with the latter reserved mainly for high-speed physical interfaces (phys) such as 622 mbps oc-12. due to the limited speed range of the cy7c924, only the 8-bit interface is implemented. utopia-1 was the original utopia specification (created in 1993) which covers transport of: 155.52 mbps (scrambled sonet/oc-3) 155.52 mbps (8b/10b block coded at 194.4 mbaud) 100 mbps (4b/5b encoded taxi) 44.736 mbps (ds-3/t3) 51.84 mbps (oc-1) the utopia-1 interface has a maximum clock rate of 25 mhz. all ac-timing and pin descriptions are covered in the utopia-1 specification, version 2.01. utopia-2 was created as an addendum to the utopia-1 specification. in this revision, the parallel interface was extend- ed to both 33 mhz and 50 mhz to accommodate pci bus ar- chitectures in atm designs. a method of addressing was add- ed to allow multiple devices (phys) to share a common host bus. also, a description of a management interface was added (not supported by this device). the cy7c924dx contains all pins necessary to support the utopia-1 and, through use of an external address decoder, can emulate the multi-phy capability of a utopia-2 interface. the maximum bus speed supports the full 50 mhz i/o rate for emerging high-performance systems. utopia address match and selection all actions on a utopia-2 interface are controlled by the ad- dress match and selection states of the interface. these states control the read and write access to the receive and transmit fifos, access to the fifo status flags, reset of the transmit and receive fifos, and read and write access to the serial address register. the cy7c924dx supports the concept of an ? address match ? through a single address match (am*) input. address match and fifo flag access the cy7c924dx makes use of a single active-low address match (am*) to generate address-match conditions. when this input is low it is equivalent to an atm address compare on both the txaddr and rxaddr buses. this allows multiple cy7c924dx devices to share a common bus, with device out- put three-state controls being managed by either an address match condition (am* sampled low), or by a selection state. the transmit and receive fifo flag output drivers are en- abled in any txclk, refclk, or rxclk cycle following am* being sampled asserted (low) by the rising edge of the re- spective clock. the am* input is sampled separately by the clocks for the transmit and receive interfaces, which allows these clocks to be both asynchronous to each other, and to operate at different clock rates. an example of both transmit and receive fifo flag access is shown in figure 8 .
cy7c924dx 42 when the transmit fifo is enabled (fifobyp* is high) or in byte-packed mode) and am* is sampled low by the rising edge of txclk, the output drivers for the txfull* and txempty* fifo flags are enabled. when am* is sampled high by the rising edge of txclk, these same output drivers are disabled. when the transmit fifo is bypassed (fifobyp* is low and not in byte-packed mode) and am* is sampled low by the rising edge of refclk, the output drivers for the txfull* and txempty* fifo flags are enabled. when am* is sam- pled high by the rising edge of refclk, the fifo flag output drivers are disabled. when am* is sampled low by the rising edge of rxclk (in- put or output), the output drivers for the rxfull* and rxempty* fifo flags are enabled. when am* is sampled high by the rising edge of rxclk, the fifo flag output driv- ers are disabled. device selection the concept of selection is used to control the access to the transmit and receive parallel-data ports of the device. there are three primary types of selection: transmit data selection (with and without internal transmit fifo) receive data selection (with and without internal receive fifo) continuous selection (for either or both transmit and receive interfaces) in addition to these normal selection types, there are two ad- ditional sequences that are used to control the internal trans- mit and receive fifos reset operations, and to control read/write access to the serial address register: transmit reset sequence receive reset sequence (includes access to the serial ad- dress register) of these operations, the transmit data selection and transmit reset sequence are mutually exclusive and cannot exist at the same time. the receive data selection and receive reset se- quence are also mutually exclusive and cannot exist at the same time. either transmit operation can exist at the same time as either receive operation. all normal forms of selection require that an address match condition must exist (am* sampled low) either at the same time as the selection control signal being sampled asserted, or one or more clock cycles prior to the selection control signal being sampled asserted. transmit data selection asynchronous with utopia timing and control (transmit fifo enabled) when am* is sampled low and txrst* is sampled high by the rising edge of txclk, a tx_match condition is generated. this tx_match condition continues until am* is sampled high or txrst* is sampled low at the rising edge of txclk. when a tx_match (or tx_rstmatch) condition is present, the txempty* and txfull* output drivers are enabled. when a tx_match (or tx_rstmatch) condition is not present, these same drivers are disabled (high-z). the selection state of the transmit fifo is entered when a tx_match condition is present, and txen* transitions from high to low. once selected, the transmit fifo remains se- lected until txen* is sampled high by the rising edge of txclk. in the selected state, data present on the txdata inputs is captured and stored in the transmit fifo. this trans- mit interface selection process is shown in figure 9 . synchronous with utopia timing and control (transmit fifo bypassed) when the transmit fifo is bypassed (fifobyp* is low and not in byte-packed mode), the cy7c924dx must still be se- lected to write data into the transmit input register. when am* is sampled low and txrst* is sampled high by the rising edge of refclk, a tx_match condition is generat- ed. this tx_match condition continues until am* is sampled high or txrst* is sampled low at the rising edge of txclk. when a tx_match (or tx_rstmatch) condition is present, the txempty* and txfull* output drivers are en- abled (with the transmit fifo bypassed, the status flags nor- mally indicate an empty condition). when a tx_match (or tx_rstmatch) condition is not present, these same drivers are disabled (high-z). the selection state of the transmit input register is entered when a tx_match condition is present, and txen* transitions from high to low. once selected, the transmit input register remains selected until txen* is sampled high by the rising edge of refclk. in the selected state, data present on the txdata inputs is captured in the transmit input register and passed to the serializer or encoder (as selected by the encbyp* input). this transmit interface selection process is shown in figure 10 . when data is not written to the transmit input register, the data stream is automatically padded with c5.0 (k28.5) sync characters. if the 8b/10b encoder is enabled, disparity track- ing allows the added c5.0 fill characters to follow all 8b/10b encoding rules. if the 8b/10b encoder is bypassed, disparity tracking is disabled, and the transition between externally en- coded data and internally generated c5.0 characters may gen- erate a running disparity error at the attached receiver. the rxclk am* rxempty* valid figure 8. fifo flag driver enables txclk am* txfull* valid transmit port addressing receive port addressing
cy7c924dx 43 figure 9. transmit selection with transmit fifo enabled [31] [31] not full txrst* am* tx_match txen* tx_selected txdata txclk d1 not full d2 d3 txfull* d1 d2 d3 (utopia timing) txdata (cascade timing) note 32 note 32 figure 10. transmit selection with transmit fifo bypassed notes: 31. signals labeled in italics are internal to the cy7c924dx. 32. signals shown as dotted lines represent the differences in timing and active state of signals when operated in cascade timin g. [31] [31] txrst* am* tx_match txen* tx_selected txfull* refclk not full not full txdata d1 d2 d3 d1 d2 d3 (utopia timing) txdata (cascade timing) note 32 note 32
cy7c924dx 44 same error may occur at the transition between the internal c5.0 characters and the resumption of externally encoded da- ta. when strings of contiguous c5.0 characters are generated, each c5.0 has alternating running disparity with the previous c5.0 character. receive data selection asynchronous with utopia timing and control (receive fifo enabled) when am* is sampled low and rxrst* is sampled high by the rising edge of rxclk input, an rx_match condition is gen- erated. this rx_match condition continues until am* is sam- pled high or rxrst* is sampled low at the rising edge of rxclk input. when an rx_match (or rx_rstmatch) condition is present, the rxempty* and rxfull* output drivers are enabled. when an rx_match (or rx_rstmatch) condition is not present, these same drivers are disabled (high-z). the selection state of the receive fifo is entered when an rx_match condition is present, and rxen* transitions from high to low. once selected, the receive fifo remains se- lected until rxen* is sampled high by the rising edge of rxclk input. the selected state initiates a read cycle from the receive fifo and enables the receive fifo data onto the rxdata bus. this receive interface selection process is shown in figure 11 . synchronous with utopia timing and control (receive fifo bypassed) when the receive fifo is bypassed (fifobyp* is low and not in a byte-packed mode), the cy7c924dx must still be se- lected to enable the output drivers for the rxdata bus. with the receive fifo bypassed, rxclk becomes a synchronous output clock operating at the character rate. when am* is sampled low and rxrst* is sampled high by the rising edge of rxclk output, an rx_match condition is generated. this rx_match condition continues until am* is sampled high or rxrst* is sampled low at the rising edge of rxclk. when an rx_match (or rx_rstmatch) condition is present, the rxempty* and rxfull* output drivers are enabled. with the receive fifo bypassed, these flags normally indi- cate a non-empty condition but may indicate empty if a c5.0 fill character is present in the output register and the receiver discard policy is non-0. when an rx_match (or rx_rstmatch) condition is not present, these same drivers are disabled (high-z). the selection state of the receive output register is entered when an rx_match condition is present, and rxen* transi- tions from high to low. once selected, the receive output register remains selected until rxen* is sampled high by the rising edge of rxclk output. in the selected state, the output drivers for the rxdata outputs are enabled, and new data is presented to the rxdata bus on every clock cycle. continuous selection continuous selection is a specialized form of selection which does not require sequenced assertion of am* and txen* or rxen* to select the device for data transfers. in this continu- ous selection mode, the am* and associated txen* or rxen* enable signal must be asserted when the device is powered up or during assertion of reset*[1:0]. so long as these signals remain asserted, the device remains selected and data is accepted and presented on every clock cycle. note: the use of continuous selection makes it impossible to reset the respective internal fifos, or to access the se- rial address register. d1 d2 d3 rxclk am* rx_match rxen rx_selected rxdata rxempty figure 11. receive selection with receive fifo enabled rxrst* not empty not empty [31] [31] note 32 note 32
cy7c924dx 45 fifo reset address match when am* and txrst* are both low, and this condition is sampled by the rising edge of txclk, a tx_rstmatch condi- tion is generated. this tx_rstmatch condition continues until am* or txrst* is sampled high by the rising edge of txclk. when a tx_rstmatch (or tx_match) condition is present, the txempty* and txfull* output drivers are enabled (just as in a normal tx_match condition). when a tx_rstmatch (or tx_match) condition is not present, these same drivers are disabled (high-z). the transmit fifo reset address match is shown in figure 12 . note that although txrst* remains low for more than one clock cycle, the tx_rstmatch does not be- cause the am* signal is no longer asserted (low). when am* and rxrst* are both low, and this condition is sampled by the rising edge of rxclk, an rx_rstmatch con- dition is generated. this rx_rstmatch condition continues un- til am* or rxrst* is sampled high, at the rising edge of rxclk. when an rx_rstmatch (or rx_match) condition is present, the rxempty* and rxfull* output drivers are en- abled. when an rx_rstmatch (or rx_match) condition is not present, these same drivers are disabled (high-z). the re- ceive fifo reset address match is shown in figure 13 . note that while the fifo flags remain asserted for more than one clock cycle, this is due to an rx_match condition, not a contin- uation of the rx_rstmatch. fifo reset sequence on power-up, the transmitter and receiver fifos are cleared automatically. if the usage of the fifos in specific operating modes results in stale or unwanted data, this data can be cleared by resetting the respective fifo. data in the transmit fifo will empty automatically if it is enabled to read the fifo (assuming txhalt* is not low). stale received data can be ? flushed ? by reading it, or the receive fifo can be reset to remove the unwanted data. the transmit and receive fifos are reset when the tx_rstmatch or rx_rstmatch condition remains present for eight consecutive clock cycles. any disruption of the reset se- quence prior to reaching the eight cycle count, either by re- moval of am* or the respective txrst* or rxrst*, or asser- tion of the associated txen* or rxen*, terminates the sequence and does not reset the fifo. because am* must remain asserted during the reset sequence, the addressed fifo flags remain driven during the entire sequence. transmit fifo reset sequence the transmit fifo reset sequence is started when txrst* and am* are first sampled low by the rising edge of txclk. however, if txen* is asserted, the reset sequence is inhibited until it is removed (txen* is sampled high for utopia timing or low for cascade timing). because a tx_rstmatch condi- tion is present, the transmit fifo flags are asserted and can be used to track the status of any transmit fifo reset in progress. once the reset sequence has reached its maximum count, the transmit fifo flags are forced to indicate a full* condition (txempty* is deasserted, and both txhalf* and txfull* are asserted). this indicates that the transmit fifo reset has been recognized by the transmit control state ma- chine and that a reset has been started. note: the fifo full state forced by the reset operation is different from a full state caused by normal fifo data writes. for normal fifo write operations, when full is first asserted, the transmit fifo must still accept up to eight additional writes of data. when a full state is asserted due to a transmit fifo reset operation, the fifo will not accept any additional data. when a transmit fifo reset sequence is enabled and has been active for at least eight txclk cycles, a transmit fifo reset operation is started. this fifo reset operation is not allowed to progress within the device until the associated txrst* is sampled deasserted (high). following deasser- tion of txrst* (which starts the fifo reset operation), selec- tion of the device for normal data transfers is inhibited during the immediately following txclk clock cycle. if a selection of the transmit interface is attempted during this immediately fol- lowing cycle (by asserting txen*), the selection is ignored, and the device remains unselected until txen* is deasserted, and reasserted in a following txclk cycle. the transmit fifo reset does not complete until the external reset condition is removed. this can be removed by deasser- tion of either txrst* or am*. if am* is deasserted (high) to remove the reset condition, the transmit fifo flag ? s drivers are disabled, and the transmit fifo must be addressed at a later time to validate completion of the transmit fifo reset. if txclk am* txfull* txrst* tx_rstmatch tx_match figure 12. transmit fifo reset address match valid [31] [31] rxclk am* rxempty rxrst* rx_rstmatch valid rx_match figure 13. receive fifo reset address match valid [31] [31]
cy7c924dx 46 txrst* is deasserted (high) to remove the reset condition, the tx_rstmatch is changed to a tx_match, and the transmit fifo status flags remain driven. the transmit fifo reset op- eration is complete when the transmit fifo flags indicate an empty state (txempty* is asserted and both txhalf* and txfull* are deasserted). a valid transmit fifo reset se- quence is shown in figure 14 . here the txrst* and am* are asserted (low) at the same time. when these signals are both sampled low by txclk, a tx_rstmatch condition is present. with txen* deasserted (high), the transmit fifo is not selected for data transfers. this tx_rstmatch condition remains for eight txclk cycles to generate the tx_fifo_reset. following this the txfull* fifo status flag is asserted to indicate that the transmit fifo reset sequence has completed and that a transmit fifo reset is in progress. when the txrst* signal is deasserted (high), am* remains low to allow the fifo status flags to be driven. this allows the completion of the reset operation to be monitored. to allow better multi-tasking on multi-phy implementations, it is possi- ble to deassert am* (high) as soon as the full state is indi- cated. the fifo reset operation will complete and the empty state (indicating completion of the reset operation) can be de- tected during a separate polling operation. for those links implemented with a single phy, it is possible to tie am* low and still perform normal accesses and reset op- erations, as shown in figure 15 . in a single-phy implementa- tion with am* always low, a transmit fifo reset can never be initiated with txen* asserted at the same time as txrst*. since am* is always low, any assertion of txen* prevents the reset sequence counter from advancing. figure 16 shows a sequence of input signals which does not produce a fifo reset. in this case txen* was asserted to select the a transmit fifo for data transfers. because txen* remains active, the assertion of am* and txrst* does not initiate a reset operation. this is shown by the txfull* flag remaining high (deasserted) following what would be the nor- mal expiration of the eight-state reset counter. receive fifo reset sequence the receive fifo reset sequence operates (for the most part) the same as the transmit fifo reset sequence. the same requirements exist for the assertion state of rxrst* and se- lection of the interface. a sample receive fifo reset se- quence is shown in figure 17 . upon recognition of a receive fifo reset, the receive fifo flags are forced to indicate an empty state to prohibit additional reads from the fifo. unlike the transmit fifo, where the internal completion of the reset operation is shown by first going full and later going empty when the internal reset is complete, there is no secondary in- dication of the completion of the internal reset of the receive fifo. the receive fifo is usable as soon as new data is placed into it by the receive control state machine. when a receive fifo reset sequence is enabled and has been active for at least eight rxclk cycles, a receive fifo reset operation is started. this fifo reset operation is not allowed to progress within the device until the associated rxrst* is sampled deasserted (high). following deasser- tion of rxrst* (which starts the fifo reset operation), selec- tion of the device for normal data transfers is inhibited during the immediately following rxclk clock cycle. if a selection of the transmit interface is attempted during this immediately fol- lowing cycle (by asserting rxen*), the selection is ignored, figure 14. transmit fifo reset sequence txclk txrst* tx_rstmatch tx_fifo_reset txfull* txen* am* tx_match not full full note 32 note 32 [31] [31] [31]
cy7c924dx 47 figure 15. transmit fifo reset sequence with constant am* txclk txrst* tx_rstmatch tx_fifo_reset txfull* txen* am* tx_match [31] [31] [31] note 32 note 32 not full full figure 16. invalid transmit fifo reset sequence with txen* asserted txclk txrst* tx_rstmatch tx_fifo_reset txfull* txen* am* tx_match [31] [31] [31] note 32 note 32 not full
cy7c924dx 48 and the device remains unselected until rxen* is deasserted, and reasserted in a following rxclk cycle. serial address register access the serial address register in the cy7b924dx is accessed through the rxdata bus. this register can be both written and read, and is accessed by asserting rxrst* to address the register in the device instead of the normal receive fifo data. within this alternate address space, the rxrvs signal is an input at all times, and is used to select between read (rxrvs is high) and write (rxrvs is low) operations on the serial address register. the serial address register is the same size as the 8- or 10- bit data width selected by byte8/10*. it can be set to match domain or multicast addresses by the level on rxsc/d*. if rxs/d* is low when the serial address register is written, it becomes the multicast address register and declares a match if any single bit (or multiple bits) matches the equivalent bit in the incoming address character. if rxsc/d* is high when the serial address register is written, it becomes the unicast ad- dress register and defines a match only if all of the bits match the incoming address character. this register mapping is shown in figure 6 . accessing serial address register to access the serial address register in the cy7b924dx, an rx_rstmatch condition must first be generated by the com- bined assertion of am* and rxrst*. rxen* is then used as the data strobe signal to initiate either a read or write cycle to the rxdata bus. if rxrvs = 1 (high) at the time of the rxen* data strobe, a register read operation takes place. if rxrvs = 0 (low) at the time of the rxen* data strobe, a register write operation takes place. the rxsc/d* input is used in conjunction with rxdata[9:0] or rxdata[7:0] to select the operational mode of the serial address register (unicast or multicast). register write and read operations are shown in figure 18 . if the serial address register write and read operations are both performed without deasserting rxrst*, then rxrst* will still not extend to the eight-cycle requirement for a reset and the receive fifo will not be reset. fifo reset and continuous selection when configured for continuous selection (am* asserted with txen* always enabled, or am* asserted with rxen* always enabled), it is not possible to reset the transmit and receive fifos. it is also not possible to write to the serial address register without deselecting the receive fifo interface. x3.230 codes and notation conventions information to be transmitted over a serial link is encoded eight bits at a time into a 10-bit transmission character and then sent serially, bit by bit. information received over a serial link is collected ten bits at a time, and those transmission characters that are used for data (data characters) are decoded into the correct eight-bit codes. the 10-bit transmission code sup- ports all 256 8-bit combinations. some of the remaining trans- mission characters (special characters) are used for func- tions other than data transmission. the primary rationale for use of a transmission code is to improve the transmission characteristics of a serial link. the encoding defined by the transmission code ensures that suf- ficient transitions are present in the serial bit stream to make clock recovery possible at the receiver. such encoding also greatly increases the likelihood of detecting any single or mul- figure 17. receive fifo reset sequence rxclk rxrst* rx_rstmatch rx_fifo_reset rxempty* rxen* am* rx_match [31] [31] [31] note 32 note 32 not empty empty
cy7c924dx 49 tiple bit errors that may occur during transmission and recep- tion of information. in addition, some special characters of the transmission code selected by fibre channel standard con- sist of a distinct and easily recognizable bit pattern (the special character comma) that assists a receiver in achieving word alignment on the incoming bit stream. notation conventions the documentation for the 8b/10b transmission code uses letter notation for the bits in an 8-bit byte. fibre channel stan- dard notation uses a bit notation of a, b, c, d, e, f, g, h for the 8-bit byte for the raw 8-bit data, and the letters a, b, c, d, e, i, f, g, h, j for encoded 10-bit data. there is a correspondence between bit a and bit a, b and b, c and c, d and d, e and e, f and f, g and g, and h and h. bits i and j are derived, respec- tively, from (a,b,c,d,e) and (f,g,h). the bit labeled a in the description of the 8b/10b transmission code corresponds to bit 0 in the numbering scheme of the fc- 2 specification, b corresponds to bit 1, as shown here: fc-2 bit designation ? 76543210 hotlink tx/rx designation ? 76543210 8b/10b bit designation ? hgf edcba to clarify this correspondence, the following example shows the conversion from an fc-2 valid data byte to a transmission character (using 8b/10b transmission code notation): fc-2 45 bits: 7654 3210 0100 0101 converted to 8b/10b notation (note carefully that the order of bits is reversed): data byte name d5.2 bits: abcde fgh 10100 010 translated to a transmission character in the 8b/10b trans- mission code: bits: abcdei fgh j 1010010101 each valid transmission character of the 8b/10b transmis- sion code has been given a name using the following conven- tion: cxx.y, where c is used to show whether the transmission character is a data character (c is set to d, and the sc/d* pin is low) or a special character (c is set to k, and the sc/d* pin is high). when c is set to d, xx is the decimal value of the binary number composed of the bits e, d, c, b, and a in that order, and the y is the decimal value of the binary number composed of the bits h, g, and f in that order. when c is set to k, xx and y are derived by comparing the encoded bit patterns of the special character to those patterns derived from encoded valid data bytes and selecting the names of the patterns most similar to the encoded bit patterns of the special character. rxclk rxrst* am* rxen* rxrvs rxempty rx_rstmatch rx_fifo_reset rxdata figure 18. serial address register access write register read register [31] [31] note 32 note 32 rxsc/d* (r/w input)
cy7c924dx 50 under the above conventions, the transmission character used for the examples above, is referred to by the name d5.2. the special character k29.7 is so named because the first six bits (abcdei) of this character make up a bit pattern similar to that resulting from the encoding of the unencoded 11101 pat- tern (29), and because the second four bits (fghj) make up a bit pattern similar to that resulting from the encoding of the unencoded 111 pattern (7). note: this definition of the 10-bit transmission code is based on (and is in basic agreement with) the following references, which describe the same 10-bit transmission code. a.x. widmer and p.a. franaszek. ? a dc-balanced, parti- tioned-block, 8b/10b transmission code ? ibm journal of re- search and development , 27, no. 5: 440-451 (september, 1983). u.s. patent 4,486,739. peter a. franaszek and albert x. wid- mer. ? byte-oriented dc balanced (0.4) 8b/10b partitioned block transmission code ? (december 4, 1984). fibre channel physical and signaling interface (ans x3.230 ? 1994 ansi fc ? ph standard). ibm enterprise systems architecture/390 escon i/o inter- face (document number sa22 ? 7202). 8b/10b transmission code the following information describes how the tables are used for both generating valid transmission characters (encoding) and checking the validity of received transmission characters (decoding). it also specifies the ordering rules to be followed when transmitting the bits within a character and the charac- ters within the higher-level constructs specified by the stan- dard. transmission order within the definition of the 8b/10b transmission code, the bit positions of the transmission characters are labeled a, b, c, d, e, i, f, g, h, j. bit ? a ? is transmitted first followed by bits b, c, d, e, i, f, g, h, and j in that order. (note that bit i is transmitted between bit e and bit f, rather than in alphabetical order.) valid and invalid transmission characters the following tables define the valid data characters and valid special characters (k characters), respectively. the tables are used for both generating valid transmission characters (en- coding) and checking the validity of received transmission characters (decoding). in the tables, each valid-data-byte or special-character-code entry has two columns that represent two (not necessarily different) transmission characters. the two columns correspond to the current value of the running disparity ( ? current rd ? ? or ? current rd+ ? ). running disparity is a binary parameter with either the value negative ( ? ) or the value positive (+). after powering on, the transmitter may assume either a posi- tive or negative value for its initial running disparity. upon transmission of any transmission character, the transmitter will select the proper version of the transmission character based on the current running disparity value, and the trans- mitter calculates a new value for its running disparity based on the contents of the transmitted character. special character codes c1.7 and c2.7 can be used to force the transmission of a specific special character with a specific running disparity as required for some special sequences in x3.230. after powering on, the receiver may assume either a positive or negative value for its initial running disparity. upon reception of any transmission character, the receiver decides whether the transmission character is valid or invalid according to the following rules and tables and calculates a new value for its running disparity based on the contents of the received char- acter. the following rules for running disparity are used to calculate the new running-disparity value for transmission characters that have been transmitted (transmitter ? s running disparity) and that have been received (receiver ? s running disparity). running disparity for a transmission character is calculated from sub-blocks, where the first six bits (abcdei) form one sub- block and the second four bits (fghj) form the other sub-block. running disparity at the beginning of the 6-bit sub-block is the running disparity at the end of the previous transmission char- acter. running disparity at the beginning of the 4-bit sub-block is the running disparity at the end of the 6-bit sub-block. run- ning disparity at the end of the transmission character is the running disparity at the end of the 4-bit sub-block. running disparity for the sub-blocks is calculated as follows: 1. running disparity at the end of any sub-block is positive if the sub-block contains more ones than zeros. it is also pos- itive at the end of the 6-bit sub-block if the 6-bit sub-block is 000111, and it is positive at the end of the 4-bit sub-block if the 4-bit sub-block is 0011. 2. running disparity at the end of any sub-block is negative if the sub-block contains more zeros than ones. it is also neg- ative at the end of the 6-bit sub-block if the 6-bit sub-block is 111000, and it is negative at the end of the 4-bit sub-block if the 4-bit sub-block is 1100. 3. otherwise, running disparity at the end of the sub-block is the same as at the beginning of the sub-block. use of the tables for generating transmission characters the appropriate encoding for the valid data byte or the special character byte into a transmission character is listed in the character encoding tables 10 and 11 . the current value of the transmitter ? s running disparity is used to select the transmis- sion character from its corresponding column. for each trans- mission character transmitted, a new value of the running dis- parity is calculated. this new value is used as the transmitter ? s current running disparity for the next valid data byte or special character byte to be encoded and transmitted. table 8 shows naming notations and examples of valid transmission charac- ters. use of the tables for checking the validity of received transmission characters the column corresponding to the current value of the receiv- er ? s running disparity is searched for the received transmis- sion character. if the received transmission character is found in the proper column, then the transmission character is valid and the associated data byte or special character code is determined (decoded). if the received transmission character is not found in that column, then the transmission character is invalid. this is called a code violation. indepen- dent of the transmission character ? s validity, the received transmission character is used to calculate a new value of running disparity. the new value is used as the receiver ? s cur- rent running disparity for the next received transmission char- acter.
cy7c924dx 51 detection of a code violation does not necessarily show that the transmission character in which the code violation was detected is in error. code violations may result from a prior error that altered the running disparity of the bit stream which did not result in a detectable error at the transmission char- acter in which the error occurred. ta b l e 9 shows an example of this behavior. table 8. valid transmission characters data byte name tx in or rx out hex value 765 43210 d0.0 000 00000 00 d1.0 000 00001 01 d2.0 000 00010 02 . . . . . . . . d5.2 010 000101 45 . . . . . . . . d30.7 111 11110 fe d31.7 111 11111 ff table 9. code violations resulting from prior errors rd character rd character rd character rd transmitted data character ? d21.1 ? d10.2 ? d23.5 + transmitted bit stream ? 101010 1001 ? 010101 0101 ? 111010 1010 + bit stream after error ? 101010 1011 + 010101 0101 + 111010 1010 + decoded data character ? d21.0 + d10.2 + code violation +
cy7c924dx 52 table 10. valid data characters (txsc/d* = low, rxsc/d* = low) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj d0.0 000 00000 100111 0100 011000 1011 d0.1 001 00000 100111 1001 011000 1001 d1.0 000 00001 011101 0100 100010 1011 d1.1 001 00001 011101 1001 100010 1001 d2.0 000 00010 101101 0100 010010 1011 d2.1 001 00010 101101 1001 010010 1001 d3.0 000 00011 110001 1011 110001 0100 d3.1 001 00011 110001 1001 110001 1001 d4.0 000 00100 110101 0100 001010 1011 d4.1 001 00100 110101 1001 001010 1001 d5.0 000 00101 101001 1011 101001 0100 d5.1 001 00101 101001 1001 101001 1001 d6.0 000 00110 011001 1011 011001 0100 d6.1 001 00110 011001 1001 011001 1001 d7.0 000 00111 111000 1011 000111 0100 d7.1 001 00111 111000 1001 000111 1001 d8.0 000 01000 111001 0100 000110 1011 d8.1 001 01000 111001 1001 000110 1001 d9.0 000 01001 100101 1011 100101 0100 d9.1 001 01001 100101 1001 100101 1001 d10.0 000 01010 010101 1011 010101 0100 d10.1 001 01010 010101 1001 010101 1001 d11.0 000 01011 110100 1011 110100 0100 d11.1 001 01011 110100 1001 110100 1001 d12.0 000 01100 001101 1011 001101 0100 d12.1 001 01100 001101 1001 001101 1001 d13.0 000 01101 101100 1011 101100 0100 d13.1 001 01101 101100 1001 101100 1001 d14.0 000 01110 011100 1011 011100 0100 d14.1 001 01110 011100 1001 011100 1001 d15.0 000 01111 010111 0100 101000 1011 d15.1 001 01111 010111 1001 101000 1001 d16.0 000 10000 011011 0100 100100 1011 d16.1 001 10000 011011 1001 100100 1001 d17.0 000 10001 100011 1011 100011 0100 d17.1 001 10001 100011 1001 100011 1001 d18.0 000 10010 010011 1011 010011 0100 d18.1 001 10010 010011 1001 010011 1001 d19.0 000 10011 110010 1011 110010 0100 d19.1 001 10011 110010 1001 110010 1001 d20.0 000 10100 001011 1011 001011 0100 d20.1 001 10100 001011 1001 001011 1001 d21.0 000 10101 101010 1011 101010 0100 d21.1 001 10101 101010 1001 101010 1001 d22.0 000 10110 011010 1011 011010 0100 d22.1 001 10110 011010 1001 011010 1001 d23.0 000 10111 111010 0100 000101 1011 d23.1 001 10111 111010 1001 000101 1001 d24.0 000 11000 110011 0100 001100 1011 d24.1 001 11000 110011 1001 001100 1001 d25.0 000 11001 100110 1011 100110 0100 d25.1 001 11001 100110 1001 100110 1001 d26.0 000 11010 010110 1011 010110 0100 d26.1 001 11010 010110 1001 010110 1001 d27.0 000 11011 110110 0100 001001 1011 d27.1 001 11011 110110 1001 001001 1001 d28.0 000 11100 001110 1011 001110 0100 d28.1 001 11100 001110 1001 001110 1001 d29.0 000 11101 101110 0100 010001 1011 d29.1 001 11101 101110 1001 010001 1001 d30.0 000 11110 011110 0100 100001 1011 d30.1 001 11110 011110 1001 100001 1001 d31.0 000 11111 101011 0100 010100 1011 d31.1 001 11111 101011 1001 010100 1001
cy7c924dx 53 d0.2 010 00000 100111 0101 011000 0101 d0.3 011 00000 100111 0011 011000 1100 d1.2 010 00001 011101 0101 100010 0101 d1.3 011 00001 011101 0011 100010 1100 d2.2 010 00010 101101 0101 010010 0101 d2.3 011 00010 101101 0011 010010 1100 d3.2 010 00011 110001 0101 110001 0101 d3.3 011 00011 110001 1100 110001 0011 d4.2 010 00100 110101 0101 001010 0101 d4.3 011 00100 110101 0011 001010 1100 d5.2 010 00101 101001 0101 101001 0101 d5.3 011 00101 101001 1100 101001 0011 d6.2 010 00110 011001 0101 011001 0101 d6.3 011 00110 011001 1100 011001 0011 d7.2 010 00111 111000 0101 000111 0101 d7.3 011 00111 111000 1100 000111 0011 d8.2 010 01000 111001 0101 000110 0101 d8.3 011 01000 111001 0011 000110 1100 d9.2 010 01001 100101 0101 100101 0101 d9.3 011 01001 100101 1100 100101 0011 d10.2 010 01010 010101 0101 010101 0101 d10.3 011 01010 010101 1100 010101 0011 d11.2 010 01011 110100 0101 110100 0101 d11.3 011 01011 110100 1100 110100 0011 d12.2 010 01100 001101 0101 001101 0101 d12.3 011 01100 001101 1100 001101 0011 d13.2 010 01101 101100 0101 101100 0101 d13.3 011 01101 101100 1100 101100 0011 d14.2 010 01110 011100 0101 011100 0101 d14.3 011 01110 011100 1100 011100 0011 d15.2 010 01111 010111 0101 101000 0101 d15.3 011 01111 010111 0011 101000 1100 d16.2 010 10000 011011 0101 100100 0101 d16.3 011 10000 011011 0011 100100 1100 d17.2 010 10001 100011 0101 100011 0101 d17.3 011 10001 100011 1100 100011 0011 d18.2 010 10010 010011 0101 010011 0101 d18.3 011 10010 010011 1100 010011 0011 d19.2 010 10011 110010 0101 110010 0101 d19.3 011 10011 110010 1100 110010 0011 d20.2 010 10100 001011 0101 001011 0101 d20.3 011 10100 001011 1100 001011 0011 d21.2 010 10101 101010 0101 101010 0101 d21.3 011 10101 101010 1100 101010 0011 d22.2 010 10110 011010 0101 011010 0101 d22.3 011 10110 011010 1100 011010 0011 d23.2 010 10111 111010 0101 000101 0101 d23.3 011 10111 111010 0011 000101 1100 d24.2 010 11000 110011 0101 001100 0101 d24.3 011 11000 110011 0011 001100 1100 d25.2 010 11001 100110 0101 100110 0101 d25.3 011 11001 100110 1100 100110 0011 d26.2 010 11010 010110 0101 010110 0101 d26.3 011 11010 010110 1100 010110 0011 d27.2 010 11011 110110 0101 001001 0101 d27.3 011 11011 110110 0011 001001 1100 d28.2 010 11100 001110 0101 001110 0101 d28.3 011 11100 001110 1100 001110 0011 d29.2 010 11101 101110 0101 010001 0101 d29.3 011 11101 101110 0011 010001 1100 d30.2 010 11110 011110 0101 100001 0101 d30.3 011 11110 011110 0011 100001 1100 d31.2 010 11111 101011 0101 010100 0101 d31.3 011 11111 101011 0011 010100 1100 table 10. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cy7c924dx 54 d0.4 100 00000 100111 0010 011000 1101 d0.5 101 00000 100111 1010 011000 1010 d1.4 100 00001 011101 0010 100010 1101 d1.5 101 00001 011101 1010 100010 1010 d2.4 100 00010 101101 0010 010010 1101 d2.5 101 00010 101101 1010 010010 1010 d3.4 100 00011 110001 1101 110001 0010 d3.5 101 00011 110001 1010 110001 1010 d4.4 100 00100 110101 0010 001010 1101 d4.5 101 00100 110101 1010 001010 1010 d5.4 100 00101 101001 1101 101001 0010 d5.5 101 00101 101001 1010 101001 1010 d6.4 100 00110 011001 1101 011001 0010 d6.5 101 00110 011001 1010 011001 1010 d7.4 100 00111 111000 1101 000111 0010 d7.5 101 00111 111000 1010 000111 1010 d8.4 100 01000 111001 0010 000110 1101 d8.5 101 01000 111001 1010 000110 1010 d9.4 100 01001 100101 1101 100101 0010 d9.5 101 01001 100101 1010 100101 1010 d10.4 100 01010 010101 1101 010101 0010 d10.5 101 01010 010101 1010 010101 1010 d11.4 100 01011 110100 1101 110100 0010 d11.5 101 01011 110100 1010 110100 1010 d12.4 100 01100 001101 1101 001101 0010 d12.5 101 01100 001101 1010 001101 1010 d13.4 100 01101 101100 1101 101100 0010 d13.5 101 01101 101100 1010 101100 1010 d14.4 100 01110 011100 1101 011100 0010 d14.5 101 01110 011100 1010 011100 1010 d15.4 100 01111 010111 0010 101000 1101 d15.5 101 01111 010111 1010 101000 1010 d16.4 100 10000 011011 0010 100100 1101 d16.5 101 10000 011011 1010 100100 1010 d17.4 100 10001 100011 1101 100011 0010 d17.5 101 10001 100011 1010 100011 1010 d18.4 100 10010 010011 1101 010011 0010 d18.5 101 10010 010011 1010 010011 1010 d19.4 100 10011 110010 1101 110010 0010 d19.5 101 10011 110010 1010 110010 1010 d20.4 100 10100 001011 1101 001011 0010 d20.5 101 10100 001011 1010 001011 1010 d21.4 100 10101 101010 1101 101010 0010 d21.5 101 10101 101010 1010 101010 1010 d22.4 100 10110 011010 1101 011010 0010 d22.5 101 10110 011010 1010 011010 1010 d23.4 100 10111 111010 0010 000101 1101 d23.5 101 10111 111010 1010 000101 1010 d24.4 100 11000 110011 0010 001100 1101 d24.5 101 11000 110011 1010 001100 1010 d25.4 100 11001 100110 1101 100110 0010 d25.5 101 11001 100110 1010 100110 1010 d26.4 100 11010 010110 1101 010110 0010 d26.5 101 11010 010110 1010 010110 1010 d27.4 100 11011 110110 0010 001001 1101 d27.5 101 11011 110110 1010 001001 1010 d28.4 100 11100 001110 1101 001110 0010 d28.5 101 11100 001110 1010 001110 1010 d29.4 100 11101 101110 0010 010001 1101 d29.5 101 11101 101110 1010 010001 1010 d30.4 100 11110 011110 0010 100001 1101 d30.5 101 11110 011110 1010 100001 1010 d31.4 100 11111 101011 0010 010100 1101 d31.5 101 11111 101011 1010 010100 1010 table 10. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cy7c924dx 55 d0.6 110 00000 100111 0110 011000 0110 d0.7 111 00000 100111 0001 011000 1110 d1.6 110 00001 011101 0110 100010 0110 d1.7 111 00001 011101 0001 100010 1110 d2.6 110 00010 101101 0110 010010 0110 d2.7 111 00010 101101 0001 010010 1110 d3.6 110 00011 110001 0110 110001 0110 d3.7 111 00011 110001 1110 110001 0001 d4.6 110 00100 110101 0110 001010 0110 d4.7 111 00100 110101 0001 001010 1110 d5.6 110 00101 101001 0110 101001 0110 d5.7 111 00101 101001 1110 101001 0001 d6.6 110 00110 011001 0110 011001 0110 d6.7 111 00110 011001 1110 011001 0001 d7.6 110 00111 111000 0110 000111 0110 d7.7 111 00111 111000 1110 000111 0001 d8.6 110 01000 111001 0110 000110 0110 d8.7 111 01000 111001 0001 000110 1110 d9.6 110 01001 100101 0110 100101 0110 d9.7 111 01001 100101 1110 100101 0001 d10.6 110 01010 010101 0110 010101 0110 d10.7 111 01010 010101 1110 010101 0001 d11.6 110 01011 110100 0110 110100 0110 d11.7 111 01011 110100 1110 110100 1000 d12.6 110 01100 001101 0110 001101 0110 d12.7 111 01100 001101 1110 001101 0001 d13.6 110 01101 101100 0110 101100 0110 d13.7 111 01101 101100 1110 101100 1000 d14.6 110 01110 011100 0110 011100 0110 d14.7 111 01110 011100 1110 011100 1000 d15.6 110 01111 010111 0110 101000 0110 d15.7 111 01111 010111 0001 101000 1110 d16.6 110 10000 011011 0110 100100 0110 d16.7 111 10000 011011 0001 100100 1110 d17.6 110 10001 100011 0110 100011 0110 d17.7 111 10001 100011 0111 100011 0001 d18.6 110 10010 010011 0110 010011 0110 d18.7 111 10010 010011 0111 010011 0001 d19.6 110 10011 110010 0110 110010 0110 d19.7 111 10011 110010 1110 110010 0001 d20.6 110 10100 001011 0110 001011 0110 d20.7 111 10100 001011 0111 001011 0001 d21.6 110 10101 101010 0110 101010 0110 d21.7 111 10101 101010 1110 101010 0001 d22.6 110 10110 011010 0110 011010 0110 d22.7 111 10110 011010 1110 011010 0001 d23.6 110 10111 111010 0110 000101 0110 d23.7 111 10111 111010 0001 000101 1110 d24.6 110 11000 110011 0110 001100 0110 d24.7 111 11000 110011 0001 001100 1110 d25.6 110 11001 100110 0110 100110 0110 d25.7 111 11001 100110 1110 100110 0001 d26.6 110 11010 010110 0110 010110 0110 d26.7 111 11010 010110 1110 010110 0001 d27.6 110 11011 110110 0110 001001 0110 d27.7 111 11011 110110 0001 001001 1110 d28.6 110 11100 001110 0110 001110 0110 d28.7 111 11100 001110 1110 001110 0001 d29.6 110 11101 101110 0110 010001 0110 d29.7 111 11101 101110 0001 010001 1110 d30.6 110 11110 011110 0110 100001 0110 d30.7 111 11110 011110 0001 100001 1110 d31.6 110 11111 101011 0110 010100 0110 d31.7 111 11111 101011 0001 010100 1110 table 10. valid data characters (txsc/d* = low, rxsc/d* = low) (continued) data byte name bits current rd ? current rd+ data byte name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj hgf edcba abcdei fghj abcdei fghj
cy7c924dx 56 table 11. valid special character codes and sequences (txsc/d* = high or rxsc/d* = high) [33, 34] s.c. byte name s.c. code name bits current rd ? current rd+ hgf edcba abcdei fghj abcdei fghj k28.0 c0.0 [35] (c00) 000 00000 001111 0100 110000 1011 k28.1 c1.0 [36] (c01) 000 00001 001111 1001 110000 0110 k28.2 c2.0 [36] (c02) 000 00010 001111 0101 110000 1010 k28.3 c3.0 [35] (c03) 000 00011 001111 0011 110000 1100 k28.4 c4.0 [36] (c04) 000 00100 001111 0010 110000 1101 k28.5 c5.0 [36, 37] (c05) 000 00101 001111 1010 110000 0101 k28.6 c6.0 [36] (c06) 000 00110 001111 0110 110000 1001 k28.7 c7.0 [36, 38] (c07) 000 00111 001111 1000 110000 0111 k23.7 c8.0 [35] (c08) 000 01000 111010 1000 000101 0111 k27.7 c9.0 [35] (c09) 000 01001 110110 1000 001001 0111 k29.7 c10.0 [35] (c0a) 000 01010 101110 1000 010001 0111 k30.7 c11.0 (c0b) 000 01011 011110 1000 100001 0111 end of frame sequence eofxx c2.1 [39] (c22) 001 00010 ? k28.5,dn.xxx0 +k28.5,dn.xxx1 code rule violation and svs tx pattern exception c0.7 [38, 40] (ce0) 111 00000 100111 1000 011000 0111 ? k28.5 c1.7 [41] (ce1) 111 00001 001111 1010 001111 1010 +k28.5 c2.7 [42] (ce2) 111 00010 110000 0101 110000 0101 running disparity violation pattern exception c4.7 [43] (ce4) 111 00100 110111 0101 001000 1010 notes: 33. all codes not shown are reserved. 34. notation for special character code name is consistent with fibre channel and escon naming conventions. special character co de name is intended to describe binary information present on i/o pins. common usage for the name can either be in the form used for describing data p atterns (i.e., c0.0 through c31.7), or in hex notation (i.e., cnn where nn = the specified value between 00h and ffh). 35. these characters have reserved meanings when command processing is enabled. this includes all operating modes where the fifo s are enabled and the discard policy is not 0. 36. these characters are used for control of escon interfaces. they can be sent as embedded commands or other markers when not o perating using escon protocols. 37. the k28.5 character is used for framing operations by the receiver. it is also the pad or fill character transmitted to main tain the serial link when no user data is available. 38. care must be taken when using this special character code. when a c7.0 is followed by a d11.x or d20.x, or when an svs (c0.7 ) is followed by a d11.x, and alias k28.5 sync character is created. these sequences can cause erroneous framing and should be avoided while rfen is high . 39. c2.1 = transmit either ? k28.5+ or +k28.5 ? as determined by current rd and modify the following transmission character by setting its least significant bit to 1 or 0. if current rd at the start of the following character is plus (+) the lsb is set to 0, and if current rd is minus ( ? ) the lsb becomes 1. this modification allows construction of x3.230:1994 ? eof ? frame delimiters wherein the second data byte is determined by the current rd. for example, to send ? eofdt ? the controller could issue the sequence c2.1 ? d21.4 ? d21.4 ? d21.4, and the hotlink transmitter will send either k28.5 ? d21.4 ? d21.4 ? d21.4 or k28.5 ? d21.5 ? d21.4 ? d21.4 based on current rd. likewise to send ? eofdti ? the controller could issue the sequence c2.1 ? d10.4 ? d21.4 ? d21.4, and the hotlink transmitter will send either k28.5 ? d10.4 ? d21.4 ? d21.4 or k28.5 ? d10.5 ? d21.4 ? d21.4 based on current rd. the receiver will never output this special character, since k28.5 is decoded as c5.0, c1.7, or c2.7, and the subsequent bytes are decoded as data. 40. c0.7 = transmit a deliberate code rule violation. the code chosen for this function follows the normal running disparity rul es. transmission of this special character has the same effect as asserting txsvs = high. the receiver outputs this special character only if the transmission c haracter being decoded is not found in the tables. 41. c1.7 = transmit negative k28.5 ( ? k28.5+) disregarding current rd. the receiver will only output this special character if k28.5 is received with the wrong running disparity. the receiver will output c1.7 if ? k28.5 is received with rd+, otherwise k28.5 is decoded as c5.0 or c2.7. 42. c2.7 = transmit positive k28.5 (+k28.5 ? ) disregarding current rd. the receiver will only output this special character if k28.5 is received with the wrong running disparity. the receiver will output c2.7 if +k28.5 is received with rd ? , otherwise k28.5 is decoded as c5.0 or c1.7. 43. c4.7 = transmit a deliberate code rule violation to indicate a running disparity violation. the receiver will only output th is special character if the transmission character being decoded is found in the tables, but running disparity does not match. this may indicate that an error occurred in a prior byte.
cy7c924dx 57 printed circuit board layout suggestions this is a typical printed circuit board layout showing example placement of power supply bypass components and other components mounted on the same side as the cy7c924dx. other layouts, including cases with components mounted on the reverse side would work as well. cy7c9689-ac outa outb inb ina refclk curseta resistor cursetb resistor rxsc/d reset 0.01 f mlc x7r 1206 chip cap (2 sites) power supply bypass 0.01 f mlc x7r 1206 chip cap (4 sites) power supply bypass 0.01 f mlc x7r power supply bypass 0.01 f mlc x7r power supply bypass 0.01 f mlc x7r power supply bypass via to v dd plane via to v ss plane cy7c924dx-ac
cy7c924dx ? cypress semiconductor corporation, 2000. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. document #: 38-00770-b ordering information ordering code package name package type operating range cy7c924dx-ac a100 100-lead thin quad flat pack commercial CY7C924DX-AI a100 100-lead thin quad flat pack industrial package diagram 100-pin thin plastic quad flat pack (tqfp) a100 51-85048-b

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